RT9262AGS RICHTEK [Richtek Technology Corporation], RT9262AGS Datasheet - Page 8

• Manufacturer Part Number: RT9262AGS
• Description: High Efficiency, Low Supply Current, Step-up DC/DC Converter
• Manufacturer: RICHTEK [Richtek Technology Corporation]

RT9262/A
www.richtek.com
8
Applications Information
Output Voltage Setting
Referring to application circuits Figure 1 to Figuer 5 the
output voltage of the switching regulator (V
set with Equation (1).
The LDO output voltage (V
with Equation (2).
And trip point of the low battery detector is 0.86V at LBI
pin of RT9262A.
Feedback Loop Design
Referring to application circuits Figure 1 to Figure 5. The
selection of R1, R2, R3, and R4 based on the trade-off
between quiescent current consumption and interference
immunity is stated below:
For applications without standby or suspend modes, lower
values of R1 to R4 are preferred. For applications
concerning the current consumption in standby or
suspend modes, the higher values of R1 to R4 are
needed. Such "high impedance feedback loops" are
sensitive to any interference, which require careful layout
and avoid any interference, e.g. probing to FB/LFB pins.
Follow Equation (1) and Equation (2).
Higher R reduces the quiescent current (Path current
A proper value of feed forward capacitor parallel with
= 1.25V/R2, and 0.86V/R3), however resistors beyond
5MW are not recommended.
sensitive to interference, layout parasitics, FB/LFB node
leakage, and improper probing to FB/LFB pins.
R1 (or R4) on Figure 1 to Figure 5 can improve the
noise immunity of the feedback loops, especially in an
improper layout. An empirical suggestion is around
100pF ~ 1nF for feedback resistors of MW, and 10nF~
0.1μF for feedback resistors of tens to hundreds kΩ.
Lower R gives better noise immunity, and is less
V
V
OUT
OUT
1
2
=
=
1 (
1 (
+
+
R
R
R
R
1
2
3
4
)
)
×
×
. 1
. 0
25
OUT2
86
V
V
of RT9262) can be set
OUT1
) can be
Preliminary
(1)
(2)
Layout Guide
A full GND plane without gap break.
V
for C2 to Pin1 and Pin6.
Minimized FB/LFB node copper area and keep far away
from noise sources.
Minimized parasitic capacitance connecting to LX and
EXT nodes, which may cause additional switching loss.
The following diagram is an example of 2-layer board
layout for application circuits Figure 1 to Figure 4.
V
to L1 inductor, when VIN is not an idea voltage source.
OUT1
IN
PRECAUTION 1: Improper probing to FB or LFB
pin will cause fluctuation at V
may
because V
rated level due to unexpected interference or
parasitics being added to FB pin.
PRECAUTION 2: Disconnecting R1 or short circuit
across R2 may also cause similar IC damage as
described in precaution 1.
PRECAUTION 3: When large R values were used
in feedback loops, any leakage in FB/LFB node
may also cause V
fluctuation, and IC damage. To be especially
highlight here is when the air moisture frozen and
re-melt on the circuit board may cause several
mA leakage between IC or component pins. So,
when large R values are used in feedback loops,
post coating, or some other moisture-preventing
processes are recommended.
to GND noise bypass - Add a 100μF capacitor close
to GND noise bypass
Q
+
damage RT9262/A and system chips
_
Prober Parasitics
OUT1
may drastically rise to an over-
OUT1
−
Short and wide connection
DS9262/A-11 March 2007
and V
V
OUT1
OUT1
R2
R1
OUT2
and V
FB Pin
voltage
OUT2
. It