GS1503BCVE2 GENNUM [Gennum Corporation], GS1503BCVE2 Datasheet - Page 78

• Manufacturer Part Number: GS1503BCVE2
• Description: HD Embedded Audio CODEC Data Sheet
• Manufacturer: GENNUM [Gennum Corporation]

Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
GS1503B HD Embedded Audio CODEC
Data Sheet
37953 - 1
Control
Item
Name
ADPG2_DET
ADPG1_DET
RSV
ECCB_ON
ECCA_ON
CASCADE
RSV
AMUTEB
AMUTEA
December 2009
Description
Audio group 2 data packet detect. When set
HIGH, audio data packets with group 2 DID have
been detected in the incoming Chroma video
data stream.
NOTE: Once this bit has been set, it will remain
set until a device reset is performed.
Audio group 1 data packet detect. When set
HIGH, audio data packets with group 1 DID have
been detected in the incoming Chroma video
data stream.
NOTE: Once this bit has been set, it will remain
set until a device reset is performed.
Not used.
Ch5-8 error correction enable. When set HIGH,
the GS1503B will perform error correction on
audio data packets for channels 5 to 8, based on
the six ECC words.
Ch1-4 error correction enable. When set HIGH,
the GS1503B will perform error correction on
audio data packets for channels 1 to 4, based on
the six ECC words.
Cascade select. When set HIGH, the GS1503B will
default to audio groups 3 and 4. When set LOW,
the GS1503B will default to audio groups 1 and 2.
NOTE: The status of the CASCADE external pin is
not updated in this register. The value
programmed in this register is logical OR'd with
the CASCADE external pin setting.
Not used.
Ch5-8 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 5
to 8 are forced to zero.
NOTE: The status of the MUTE external pin is not
updated in this register. The value programmed
in this register is logical OR'd with the MUTE
external pin setting.
Ch1-4 audio mute enable. When set HIGH, the
multiplexed audio packets for audio channels 1
to 4 are forced to zero.
NOTE: The status of the MUTE external pin is not
updated in this register. The value programmed
in this register is logical OR'd with the MUTE
external pin setting.
Address
013
013
013
013
013
014
014
014
014
Bit
3-2
5
4
1
0
7
6
5
4
R/W
R/W
R/W
R/W
R/W
R/W
R
R
–
–
Default
78 of 90
0
0
0
1
1
0
0
0
0