ADUM1280 AD [Analog Devices], ADUM1280 Datasheet - Page 13

• Manufacturer Part Number: ADUM1280
• Description: 3 kV RMS Dual Channel Digital Isolators
• Manufacturer: AD [Analog Devices]

Data Sheet
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at both input and output supply pins
V
between 0.01 µF and 0.1 µF. The total lead length between both
ends of the capacitor and the input power supply pin should not
exceed 20 mm.
The
FCC Class A) emissions standards, as well as the more
stringent CISPR 22 Class B (and FCC Class B) standards in
an unshielded environment, with proper PCB design choices.
Refer to the
Control of Radiated Emissions with iCoupler Devices for PCB-
related EMI mitigation techniques, including board layout and
stack-up issues.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high
transition.
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM128x
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple
components operating under the same conditions.
DD1
INPUT (V
OUTPUT (V
ADuM128x
ADuM128x
and V
Ix
)
Ox
DD2
AN-1109
component.
)
(see Figure 12). The capacitor value should be
Figure 12. Propagation Delay Parameters
digital isolator requires no external interface
can readily meet CISPR 22 Class A (and
Applicaton Note, Recommendations for
t
PLH
t
PHL
ADuM128x
50%
50%
Rev. 0 | Page 13 of 16
ADuM1280/ADuM1281/ADuM1285/ADuM1286
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent via the transformer to
the decoder. The decoder is bistable and is, therefore, either set
or reset by the pulses indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1.6 µs,
a periodic set of refresh pulses indicative of the correct input
state are sent to ensure dc correctness at the output.
If the decoder receives no pulses for more than about 6.4 µs, the
input side is assumed to be unpowered or nonfunctional, in which
case, the isolator output is forced to a default low state by the
watchdog timer circuit.
The limitation on the device’s magnetic field immunity is set
by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines such conditions. The
ADuM1280
represents the most susceptible mode of operation of this product.
The pulses at the transformer output have an amplitude greater
than 1.5 V. The decoder has a sensing threshold of about 1.0 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
where:
β is the magnetic flux density.
r
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 13.
n
is the radius of the n
0.001
V = (−dβ/dt)∑πr
0.01
100
Figure 13. Maximum Allowable External Magnetic Flux Density
0.1
10
1
1k
is examined in a 3 V operating condition because it
10k
MAGNETIC FIELD FREQUENCY (Hz)
n
2
th
; n = 1, 2, …, N
turn in the receiving coil.
100k
1M
10M
ADuM1280
100M
and