SC480 SEMTECH [Semtech Corporation], SC480 Datasheet - Page 12

• Manufacturer Part Number: SC480
• Description: Complete DDR1/2/3 Memory Power Supply
• Manufacturer: SEMTECH [Semtech Corporation]

Power Good Output
The VDDQ controller has a power good (PGD) output.
Power good is an open-drain output and requires a pull-
up resistor. When the output voltage is +16%/-10% from
its nominal voltage, PGD gets pulled low. It is held low
until the output voltage returns to within +16%/-10% of
nominal. PGD is also held low during start-up and will not
be allowed to transition high until soft-start is over and the
output reaches 90% of its set voltage. There is a 5μs delay
built into the PGD circuit to prevent false transitions.
Output Over-Voltage Protection
When the VDDQ output exceeds 16% of its set voltage,
the low-side MOSFET is latched on. It stays latched and
the SMPS stays off until the EN/PSV input is toggled or
VCCA is recycled. There is a 5μs delay built into the OV
protection circuit to prevent false transitions. During a
VDDQ OV shutdown, VTT is alive until VDDQ falls to typically
0.4V, at which point VTT is tri-stated.
When VTT exceeds 12% above its set voltage, the VTT
regulator will tristate. There is a 50μs delay to prevent false
OV trips due to transients or noise. The VDDQ regulator
continues to operate after VTT OV shutdown. The VTT OV
condition is removed by toggling VTTEN or EN/PSV, or by
recycling VCCA.
Smart Over-Voltage Protection
In some applications, the active loads on VDDQ can
actually leak current into VDDQ. If PSAVE mode is enabled
at very light loading, this leak can cause VDDQ to slowly
rise and reach the OV threshold, causing a hard shutdown.
To prevent this, the SC480 uses Smart OVP to prevent
this. When VDDQ exceeds 8% above nominal, DL drives
high to turn on the low-side MOSFET, which starts to draw
current from VDDQ via the inductor. When VDDQ drops
to the FB trip point, a normal TON switching cycle begins.
This prevents a hard OV shutdown.
Output Under-Voltage Protection
When VDDQ falls 30% below its set point for eight clock
cycles, the VDDQ output is shut off; the DL/DH drives are
pulled low to tristate the MOSFETS, and the SMPS stays
off until the Enable input is toggled or VCCA is recycled.
When VTT is 12% below its set voltage the VTT output is
tristated. There is a 50μs delay for VTT built into the UV
protection circuits to prevent false transitions.
© 2006 Semtech Corp.
POWER MANAGEMENT
POWER MANAGEMENT
Application Information (Cont.)
12
POR, UVLO and Soft-Start
An internal power-on reset (POR) occurs when VCCA ex-
ceeds 3V, resetting the fault latch and soft-start counter,
and preparing the PWM for switching. VCCA under-voltage
lockout (UVLO), circuitry inhibits switching and tristates the
drivers until VCCA rises above 4.2V. At this time the circuit
will come out of UVLO and begin switching and the soft-
start circuit will progressively limit the output current over
a pre-determined time period. The ramp occurs in four
steps: 25%, 50%, 75% and 100%, thereby limiting the slew
rate of the output voltage. There is 100mV of hysteresis
built into the UVLO circuit and when VCCA falls to 4.1V the
output drivers are shutdown and tristated.
MOSFET Gate Drivers
The DH and DL drivers are optimized for moderate, high-
side, and larger low-side power MOSFETs. An adaptive
dead-time circuit monitors the DL output and prevents the
high-side MOSFET from turning on until DL is fully off, and
conversely, monitors the DH output and prevents the low-
side MOSFET from turning on until DH is fully off.
be sure there is low resistance and low inductance between the
DH and DL outputs to the gate of each MOSFET.)
Design Procedure
Prior to designing a switch mode supply for a notebook com-
puter, the input voltage, load current, switching frequency
and inductor ripple current must be specifi ed.
Input Voltage Range
The maximum input voltage (VIN
highest AC adaptor voltage. The minimum input voltage
(VIN
accounting for voltage drops due to connectors, fuses and
battery selector switches.
Maximum Load Current
There are two values of load current to consider: continu-
ous load current and peak load current. Continuous load
current has more to do with thermal stresses and there-
fore drives the selection of input capacitors, MOSFETs
and commutation diodes. Peak load current determines
instantaneous component stresses and fi ltering require-
ments such as, inductor saturation, output capacitors and
design of the current limit circuit.
MIN
) is determined by the lowest battery voltage after
MAX
) is determined by the
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(Note: