ISPLSI2064VL-100LJ44 LATTICE [Lattice Semiconductor], ISPLSI2064VL-100LJ44 Datasheet
ISPLSI2064VL-100LJ44
Related parts for ISPLSI2064VL-100LJ44
ISPLSI2064VL-100LJ44 Summary of contents
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Features • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, ...
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Functional Block Diagram Figure 1. ispLSI 2064VL Functional Block Diagram (64-I/O and 32-I/O Versions) Input Bus Output Routing Pool (ORP) Megablock I I/O 2 I/O 3 I/O 4 I/O 5 Global Routing Pool ...
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Absolute Maximum Ratings Supply Voltage V cc ................................................. Input Voltage Applied ................................... -0.5 to +4.05V Off-State Output Voltage Applied ................ -0.5 to +4.05V Storage Temperature ..................................... -65 to 150 C Case Temp. with Power Applied .................... -55 to 125 C ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.15V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION A 250 ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 t pd2 A 2 Data Propagation Delay Clock Frequency with Internal Feedback max f — 4 Clock Frequency ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset Y0,1,2 GOE 0 Derivations of su, h and co from the Product Term Clock Logic + Reg ...
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Power Consumption Power consumption in the ispLSI 2064VL device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 100 I CC ...
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Signal Descriptions Signal Name RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one ...
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Signal Locations ...
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Signal Configuration ispLSI 2064VL 100-Ball caBGA Signal Diagram 10 9 I/O I I/O I I/O I I/O I GOE F VCC 0 TCK/ ...
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Pin Configuration ispLSI 2064VL 100-Pin TQFP Pinout Diagram RESET 11 VCC ...
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Pin Configuration ispLSI 2064VL 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 Pin Configuration ispLSI 2064VL 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O ...
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Part Number Description ispLSI 2064VL XXX X XXXX Device Family Device Number Speed f 165 = 165 MHz max f 135 = 135 MHz max f 100 = 100 MHz max ispLSI 2064VL Ordering Information FAMILY fmax (MHz) tpd (ns) ...