ISPLSI2096E-180LQ128 LATTICE [Lattice Semiconductor], ISPLSI2096E-180LQ128 Datasheet - Page 5

• Manufacturer Part Number: ISPLSI2096E-180LQ128
• Manufacturer: LATTICE [Lattice Semiconductor]

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Timing Parameters
PARAMETER
pd1
pd2
max
max (Ext.)
max (Tog.)
su1
co1
h1
su2
co2
h2
r1
rw1
ptoeen
ptoedis
goeen
goedis
wh
wl
COND.
TEST
A
A
A
A
A
B
C
B
C
–
–
–
–
–
–
–
–
–
–
4
10 GLB Reg Clk to Output Delay
11 GLB Reg Hold Time after Clk
12 External Reset Pin to Output Delay
13 External Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synch Clk Pulse Duration, High
19 External Synch Clk Pulse Duration, Low
#
1 Data Prop Delay, 4PT Bypass, ORP Bypass
2 Data Prop Delay
3 Clk Freq with Internal Feedback
4 Clk Freq with External Feedback
5 Clk Frequency, Max. Toggle
6 GLB Reg Setup Time before Clk, 4 PT Bypass
7 GLB Reg Clk to Output Delay, ORP Bypass
8 GLB Reg Hold Time after Clk, 4 PT Bypass
9 GLB Reg Setup Time before Clk
2
Over Recommended Operating Conditions
DESCRIPTION
1
5
3
(
tsu2 + tco1
1
Specifications ispLSI 2096E
)
MIN.
125
200
180
4.0
0.0
5.0
0.0
4.0
2.5
2.5
–
–
–
–
–
–
–
–
–
-180
MAX.
10.0
10.0
7.5
5.0
3.0
3.5
7.0
5.0
5.0
–
–
–
–
–
–
–
–
–
–
MIN.
135
100
143
5.0
0.0
6.0
0.0
5.0
3.5
3.5
–
–
–
–
–
–
–
–
–
-135
MAX.
10.0
10.0
12.0
12.0
7.5
4.0
4.5
7.0
7.0
–
–
–
–
–
–
–
–
–
–
MIN. MAX.
100
100
6.5
0.0
8.0
0.0
6.5
5.0
5.0
77
–
–
–
–
–
–
–
–
–
-100
Table 2-0030A/2096E
10.0
13.0
13.5
15.0
15.0
5.0
6.0
9.0
9.0
–
–
–
–
–
–
–
–
–
–
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns