GAL20LV8D-7LJ LATTICE [Lattice Semiconductor], GAL20LV8D-7LJ Datasheet - Page 14

• Manufacturer Part Number: GAL20LV8D-7LJ
• Description: Low Voltage E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

An electronic signature is provided in every GAL20LV8D device.
It contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter the checksum.
A security cell is provided in the GAL20LV8D devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.
GAL20LV8D devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots.
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.
Electronic Signature
Security Cell
Latch-Up Protection
Device Programming
14
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
GAL20LV8D devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing text vectors
perform output register preload automatically.
GAL20LV8D devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The GAL20LV8D input and I/O pins have built-in active pull-ups.
As a result, unused inputs and I/Os will float to a TTL “high”
(logical “1”). Lattice Semiconductor recommends that all unused
inputs and tri-stated I/O pins be connected to another active input,
V
and reduce I
Output Register Preload
Input Buffers
CC
, or Ground. Doing this will tend to improve noise immunity
-10
-20
-30
-40
-50
-60
-70
-80
0
Specifications GAL20LV8
CC
Typical Input Pull-up Characteristic
for the device.
Input Voltage (V)