GAL22LV10C-10LJ LATTICE [Lattice Semiconductor], GAL22LV10C-10LJ Datasheet - Page 14

• Manufacturer Part Number: GAL22LV10C-10LJ
• Manufacturer: LATTICE [Lattice Semiconductor]

Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1 s MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
Typ. Vref = Vcc
INPUT/OUTPUT EQUIVALENT SCHEMATICS
POWER-UP RESET
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
(GAL22LV10D Only)
Active Pull-up Circuit
Typical Input
INTERNAL REGISTER
OUTPUT REGISTER
OUTPUT REGISTER
Vref
ACTIVE HIGH
ACTIVE LOW
Q - OUTPUT
C L K
V c c
Vcc
Vcc
Vcc (min.)
14
t
pr
chronous nature of system power-up, some conditions must be
met to provide a valid power-up reset of the GAL22V10. First, the
Vcc rise must be monotonic. Second, the clock input must be at
static TTL level as shown in the diagram during power up. The
registers will reset within a maximum of tpr time. As in normal sys-
tem operation, avoid clocking the device until all input and feed-
back path setup times have been met. The clock must also meet
the minimum pulse width requirements.
Typ. Vref = Vcc
Data
Output
Specifications GAL22LV10
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
t
wl
t
su
Feedback
Tri-State
Control
Typical Output
Vcc
(GAL22LV10D Only)
Active Pull-up Circuit
Feedback
(To Input Buffer)
Vref
PIN
PIN