AS7C1026B-10JC ALSC [Alliance Semiconductor Corporation], AS7C1026B-10JC Datasheet - Page 7

• Manufacturer Part Number: AS7C1026B-10JC
• Description: 5 V 64K X 16 CMOS SRAM
• Manufacturer: ALSC [Alliance Semiconductor Corporation]

AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 N/A.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
3/26/04, v 1.3
During V
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
These parameters are specified with C
This parameter is guaranteed, but not tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
– Output load: see Figure B.
– Input pulse level: GND to 3.5 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5
+3.5V
GND
CC
power-up, a pull-up resistor to V
10%
Figure A: Input pulse
90%
2 ns
90%
L
= 5 pF, as in Figures B. Transition is measured ± 500 mV from steady-state voltage.
10%
CC
on CE is required to meet I
Alliance Semiconductor
Figure B: 5 V Output load
D
OUT
255 Ω
SB
specification.
®
+5 V
480 Ω
C
GND
13
D
OUT
Thevenin Equivalent:
168 Ω
+1.728 V
AS7C1026B
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