AS7C1028 ALSC [Alliance Semiconductor Corporation], AS7C1028 Datasheet - Page 6

• Manufacturer Part Number: AS7C1028
• Description: 5V 256K X 4 CMOS SRAM (Common I/O)
• Manufacturer: ALSC [Alliance Semiconductor Corporation]

12/5/06; V.1.0
AC test conditions
Notes:
1
2
3
4
5
6
7
8
9
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
- Output load: see Figure B or Figure C.
- Input pulse level: GND to
- Input rise and fall times: 3 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
GND
During V
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
V
CC
10%
CC
Figure A: Input pulse
90%
power-up, a pull-up resistor to V
3 ns
90%
V
10%
CC
. See Figure A.
CC
on CE is required to meet I
Alliance Memory
D
out
255
Figure B: Output load
Ω
SB
specification.
®
+5V
480
C(13)
GND
Ω
±
200mV from steady-state voltage.
Figure C: Output load
D
Thevenin equivalent
D
out
out
350
Ω
168
Ω
+1.72V (5V)
V
320
C(13)
GND
CC
Ω
P. 6 of 8
AS7C1028