DP8420A National Semiconductor, DP8420A Datasheet
DP8420A
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DP8420A Summary of contents
Page 1
... The DP8420A 21A 22A dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8420A 21A 22A gen- erate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to auto- ...
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... Common Port A and Port B Dual Port Functions GRANTB Output LOCK Input 11 0 ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS TIMING PARAMETERS 14 0 FUNCTIONAL DIFFERENCES BETWEEN THE DP8420A 21A 22A AND THE DP8420 DP8420A 21A 22A USER HINTS 2 and t RAH ASC and t ...
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... DP8420A 21A 22A to DRAM arrays Mbytes in size After power up the user must first reset and program the DP8420A 21A 22A before accessing the DRAM The chip is programmed through the address bus Reset Due to the differences in power supplies the internal reset ...
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... Connection Diagrams Top View FIGURE 2 Order Number DP8420AV-20 or DP8420AV-25 See NS Package Number V68A Order Number DP8422AV-20 or DP8422AV- 8588–4 Order Number DP8421AV-20 or DP8421AV-25 See NS Package Number V68A Top View FIGURE 4 See NS Package Number V84A 8588– 3 Top View FIGURE 3 ...
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... ECAS0 is negated during programming this output will function as RFRQ When asserted this pin specifies that have passed If DISRFSH is negated the DP8420A 21A 22A will perform an internal refresh as soon as possible If DISRFRSH is asserted RFRQ can be used to externally request a refresh through ...
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... RAS outputs are negated for that refresh REFRESH This input asserted with DISRFRSH already asserted will request a refresh If this input is continually asserted the DP8420A 21A 22A will perform refresh cycles in a burst refresh fashion until the input is negated If RFSH is asserted ...
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... CC GND I CAP CLOCK INPUTS There are two clock inputs to the DP8420A 21A 22A CLK and DELCLK These two clocks may both be tied to the same clock input or they may be two separate clocks running at different frequencies asynchronous to each other CLK I DELCLK I Description ...
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... DISRFSH at least one clock period before negating ML as shown in Figure 5b ML negated will program the DP8420A 21A 22A with the values in R0– 9 C0– – 1 and ECAS0 The 60 ms initialization period will be entered since it is the first programming after reset This is a good ...
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... ECAS0 inputs then ML is negated When ML is negat- ed the programming bits are latched into the internal pro- gramming register and the DP8420A 21A 22A is pro- grammed see Figure 6 When programming the chip the controller must not be refreshing RFIP must be high (1) to ...
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Programming and Resetting 3 3 PROGRAMMING BIT DEFINITIONS Symbol ECAS0 Extend CAS Refresh Request Select 0 The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB DP8422A only) is negated The WE output pin ...
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Programming and Resetting 3 3 PROGRAMMING BIT DEFINITIONS (Continued) Symbol RAS and CAS Configuration Modes (Continued RAS and CAS pairs are selected by B1 ECASn must be asserted for CASn to be ...
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Programming and Resetting 3 3 PROGRAMMING BIT DEFINITIONS (Continued) Symbol R5 R4 WAIT DTACK during Burst (See Section WAIT STATES during programming WAIT will remain ...
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... Port A Access Modes The DP8420A 21A 22A have two general purpose access modes Mode 0 RAS synchronous and Mode 1 RAS asyn- chronous One of these modes is selected at programming through the B1 input A Port A access to DRAM is initiated by two input signals ADS (ALE) and CS The access is al- ...
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Port A Access Modes (Continued ACCESS MODE 1 Mode 1 asynchronous access is selected by asserting the input B1 during programming (B1 1) This mode allows ac- e cesses to start immediately from the access request ...
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Port A Access Modes (Continued EXTENDING CAS WITH EITHER ACCESS MODE In both access modes once AREQ is negated RAS and DTACK if programmed will be negated If ECAS0 was as- serted (0) during programming CAS ...
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Port A Access Modes (Continued READ-MODIFY-WRITE CYCLES WITH EITHER ACCESS MODE There are 2 methods by which this chip can be used to do read-modify-write access cycles The first method involves doing a late write access ...
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... ADDITIONAL ACCESS SUPPORT FEATURES To support the different modes of accessing DP8420A 21A 22A offer other access features These ad- ditional features include Address Latches and Column In- crement (for page burst mode support) Address Pipelining and Delay CAS (to allow the user with a multiplexed bus to ...
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... AREQ is negated WAIT if programmed will be asserted once ADS is asserted In either mode with either type of wait programmed the DP8420A 21A 22A will still delay the access for precharge if sequential accesses are to the same bank refresh takes place FIGURE 11b Address Pipelined Mode 8588– ...
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Port A Access Modes (Continued) 19 ...
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Port A Access Modes (Continued Delay CAS during Write Accesses Address bit C9 asserted during programming will cause CAS to be delayed until the first positive edge of CLK after RAS is asserted when the ...
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... The refresh address counter will be incremented once all the refresh RASs have been negated Explanation of Terms RFRQ ReFresh ReQuest internal to the DP8420A 21A 22A RFRQ has the ability to hold off a pending access e RFSH Externally requested ReFreSH e ...
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... If the user desires to burst refresh the entire DRAM (all row addresses) he could generate an end of count signal (burst refresh finished) by looking DP8420A 21A 22A high address outputs ( Q10) and the RFIP output The Qn outputs function as a decode of how many row addresses have been refreshed (Q7 128 refreshes Q8 256 refreshes Q9 ...
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... Refresh Options (Continued Refresh Request Acknowledge The DP8420A 21A 22A can be programmed to output in- ternal refresh requests When the user programs ECAS0 negated (1) and or address pipelining mode is selected the WE output functions as RFRQ RFRQ (WE) will be asserted by one of two events First when the external circuitry pulses low the input RFSH ...
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Refresh Options (Continued) 24 ...
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Refresh Options (Continued REFRESH CYCLE TYPES Three different types of refresh cycles are available for use The three different types are mutually exclusive and can be used with any of the three modes of refresh control ...
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... WE is negated The DP8422A has a 24-bit internal refresh address counter that contains the 11 row 11 column and 2 bank addresses The DP8420A 21A have a 22-bit internal refresh address coun- ter that contains the 10 row 10 column and 2 bank address- es These counters are configured as bank column row ...
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... DP8420A 21A 22A will clear the refresh address counter and then perform refresh cycles separated by the programmed value of precharge as shown in Figure 20b An end-of-count signal can be generated from the Q DRAM address outputs of the DP8420A 21A 22A and used to ne- gate RFSH TL F 8588 – 8588 – ...
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... GRANTB not being valid (DP8422A only) If one of these events is taking place and the CPU starts an access the DP8420A 21A 22A will insert wait states into the access cycle thereby increasing the refresh request clock the user is guaranteed that an inter- ...
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Port A Wait State Support 6 2 DTACK TYPE OUTPUT With the R7 address bit asserted during programming the user selects the DTACK type output As long as DTACK is sampled negated by the CPU wait states are ...
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... DP8420A 21A 22A Each RAS output has a separate posi- FIGURE 25 Guaranteeing RAS Precharge (DTACK is Sampled at the ‘‘T2’’ Falling Clock Edge) (Continued) tive edge of CLK counter AREQ is negated setup to a posi- tive edge of CLK to terminate the access That positive ...
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... DRAMs representing four banks of DRAM with 16-bit words and 2 parity bits The DP8420A 21A 22A can drive more than 72 DRAMs but the AC timing must be increased Since the RAS and CAS out- puts are configurable all RAS and CAS outputs should be ...
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RAS and CAS Configuration Modes FIGURE 26c DRAM Array Setup for 16-Bit System ( FIGURE 26d 8 Bank DRAM Array for 16-Bit System ( (Continued during Programming ...
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... MEMORY INTERLEAVING Memory interleaving allows the cycle time of DRAMs to be reduced by having sequential accesses to different memory banks Since the DP8420A 21A 22A have separate pre- charge counters per bank sequential accesses will not be delayed if the accessed banks use different RAS outputs ...
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RAS and CAS Configuration Modes FIGURE 28a DRAM Array Setup for 4 Banks Using Address Pipelining ( (Also Allowing Error Scrubbing) during Programming) e FIGURE 28b DRAM Array Setup ...
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... Nibble mode values for R and C assume a system using 1 Mbit DRAMs FIGURE 30 Page Static Column Nibble Mode System (Continued) gled with the DP8420A 21A 22A’s address latches in fall- through mode while AREQ is asserted The ECAS inputs can also be used to select individual bytes When using nib- ...
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... Test Mode Staggered refresh in combination with the error scrubbing mode places the DP8420A 21A 22A in test mode In this mode the 24-bit refresh counter is divided into a 13-bit and 11-bit counter During refreshes both counters are incre- mented to reduce test time 9 0 DRAM Critical Timing ...
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Dual Accessing (DP8422A) The DP8422A has all the functions previously described In addition to those features the DP8422A also has the capa- bilities to arbitrate among refresh Port A and a second port Port B This allows two ...
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Dual Accessing (DP8422A PORT B WAIT STATE SUPPORT Advanced transfer acknowledge for Port B ATACKB is used for wait state support for Port B This output will be asserted when RAS for the Port B access ...
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Dual Accessing (DP8422A) Since the DP8422A has only one set of address inputs the signal is used with the addition of buffers to allow the cur- rently granted port’s addresses to reach the DP8422A The signals which need ...
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Dual Accessing (DP8422A) FIGURE 34b Wait States during a Port B Access LOCK Input When the LOCK input is asserted the currently granted port can ‘‘lock out’’ the other port through the insertion of wait ...
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... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Temperature under Bias Storage Temperature Electrical Characteristics Symbol Parameter V Logical 1 Input Voltage IH V Logical 0 Input Voltage and WE Outputs ...
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... AC Timing Parameters Two speed selections are given the DP8420A 21A 22A-20 and the DP8420A 21A 22A-25 The differences between the two parts are the maximum operating frequencies of the input CLKs and the maximum delay specifications Low fre- quency applications may use the ‘‘ ...
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AC Timing Parameters Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except ...
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AC Timing Parameters Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except ...
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AC Timing Parameters Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except ...
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AC Timing Parameters Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except ...
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AC Timing Parameters FIGURE 38 100 Port A and Port B Dual Access (Continued) FIGURE 37 100 Dual Access Port 8588 – 8588 – F1 ...
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AC Timing Parameters Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except ...
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AC Timing Parameters Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except ...
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AC Timing Parameters (Continued) FIGURE 40 300 Mode 0 Timing 8588 – F3 ...
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AC Timing Parameters (Programmed (Continued) FIGURE 41 300 Mode 0 Interleaving 8588 – F4 ...
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AC Timing Parameters Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except ...
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AC Timing Parameters (Continued) FIGURE 42 400 Mode 1 Timing 8588 – F5 ...
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AC Timing Parameters FIGURE 43 400 COLINC Page Static Column Access Timing (Continued 8588 – F6 ...
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AC Timing Parameters Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except ...
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AC Timing Parameters Unless otherwise stated 10 DRAMs per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except e L ...
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... were pro- grammed DP8420A 21A 22A User Hints 1 All inputs to the DP8420A 21A 22A should be tied high low or the output of some other device Note One signal is active high COLINC (EXTNDRF) should be tied low to disable ...
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... Physical Dimensions inches (millimeters) Order Number DP8420AV-20 DP8420AV-25 DP8421AV-20 or DP8421AV-25 Order Number DP8422AV-20 or DP8422AV-25 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein ...