CAT93C46 Catalyst Semiconductor, CAT93C46 Datasheet - Page 5

• Manufacturer Part Number: CAT93C46
• Description: 1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM
• Manufacturer: Catalyst Semiconductor

DEVICE OPERATION
The CAT93C46/56(57)66/86 is a 1024/2048/4096/
16,384-bit nonvolatile memory intended for use with
industry standard microprocessors. The CAT93C46/56/
57/66/86 can be organized as either registers of 16 bits
or 8 bits. When organized as X16, seven 9-bit instruc-
tions for 93C46; seven 10-bit instructions for 93C57;
seven 11-bit instructions for 93C56 and 93C66; seven
13-bit instructions for 93C86; control the reading, writing
and erase operations of the device. When organized as
X8, seven 10-bit instructions for 93C46; seven 11-bit
instructions for 93C57; seven 12-bit instructions for
93C56 and 93C66: seven 14-bit instructions for 93C86;
control the reading, writing and erase operations of the
device. The CAT93C46/56/57/66/86 operates on a single
power supply and will generate on chip, the high voltage
required during any write operation.
Instructions, addresses, and write data are clocked into
Figure 1. Sychronous Data Timing
Figure 2a. Read Instruction Timing (93C46)
DO
SK
CS
DI
DO
CS
SK
DI
1
t CSS
1
0
HIGH-Z
VALID
A N
t DIS
A N–1
t SKHI
t PD0
t DIS
A 0
t SKLOW
0
5
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
D N
VALID
D N–1
t DIH
t PD0, t PD1
DATA VALID
D 1
D 0
t HZ
t CSH
STANDBY
t CSMIN
Doc. No. 25056-00 2/98 M-1
t CS
HIGH-Z
93C46/56/57/66/86 F03
93C46/56/57/66/86 F04