ADUC844 Analog Devices, ADUC844 Datasheet
ADUC844
Related parts for ADUC844
ADUC844 Summary of contents
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... Embedded 62kB FLASH MCU FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The ADuC844 is a complete smart transducer front end, integrating two high resolution sigma-delta ADCs, an 8-bit MCU, and program/data Flash/EE memory on a single chip. The two independent ADCs (primary and auxiliary) include a temperature sensor and a PGA (allowing direct measurement of low level signals) ...
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... PRELIMINARY TECHNICAL DATA ADuC844 SPECIFICATIONS PARAMETER PRIMARY ADC Conversion Rate 2 No Missing Codes Resolution Output Noise Integral Non Linearity 3 Offset Error Offset Error Drift (vs. Temp) 4 Full-Scale Error 5 Gain Error Drift (vs. Temp) ADC Range Matching Power Supply Rejection Common Mode DC Rejection On AIN ...
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... ADuC844 CONDITION 20 Hz Update Rate Range = ± 2.5V, 20Hz Update Rate Output Noise varies with selected Update Rates 1 LSB 16 AIN=1V, Range=± 2.56V 50/60Hz ± 1Hz, 19.79Hz Update Rate 50/60Hz ± 1Hz, 19.79Hz Update Rate REFIN=REFIN(+)-REFIN(-) (or Int 1.25V Ref) REFIN=REFIN(+)-REFIN(-) (or Int 1 ...
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... PRELIMINARY TECHNICAL DATA ADuC844 SPECIFICATIONS PARAMETER INT REFERENCE ADC Reference Reference Voltage Power Supply Rejection Reference Tempco DAC Reference Reference Voltage Power Supply Rejection Reference Tempco TEMPERATURE SENSOR Accuracy Thermal Impedance TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current AIN- Current Initial Tolerance at 25°C ...
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... V 2.4 V 0.8 V 0.8 V 0.8 V +/- 300 -5- ADuC844 CONDITION 0V, DV =5V, Internal Pullup = ...
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... PRELIMINARY TECHNICAL DATA ADuC844 SPECIFICATIONS PARAMETER FLAH/EE MEMORY RELIABILITY CHARACTERISTICS 16 Endurance 17 Data Retention POWER REQUIREMENTS Power Supply Voltages AV 3V Nominal Nominal Nominal Nominal DD 5V POWER CONSUMPTION 18, 19 Normal Mode DV Current DD AV Current DD 18, 19 Power-Down Mode DV Current DD DV Current ...
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... In bipolar mode, the Auxiliary ADC can only be driven to a minimum of AGND – indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV. 12 The ADuC844BCP (CSP Package) has been qualified and tested with the base of the CSP Package floating. 13 Pins configured in SPI Mode, pins configured as digital inputs during this test. ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AGND and DGND are shorted internally on the ADuC844. 3 Applies to P1.2 to P1.7 pins operating in analog or digital input modes. Temperature MODEL ...
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... Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this input pin. I Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin. -9- ADuC844 ...
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... PRELIMINARY TECHNICAL DATA ADuC844 Pin No: Pin No: Pin 52-MQFP 56-CSP Mnemonic P3.0 à P3.7 16-19 18-21 22-25 24- P3.0/RXD 17 19 P3.1/TXD 18 20 P3.2/INT0 19 21 P3.3/INT1 22 24 P3.4/T0/PWMCLK 23 25 P3.5/ P3.6/ P3.7/RD 20, 34, 48 22, 36, 51 DVDD 21, 35, 47 23, 37, 50 DGND 26 28 SCLOCK 27 29 MOSI/SDATA 28 à à 32 P2.0 à P2.7 36 à à ...
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... An external pull-up resistor will be required on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-ups when emitting 1s. -11- ADuC844 ...
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... PRELIMINARY TECHNICAL DATA ADuC844 DETAILED BLOCK DIAGRAM WITH PIN NUMBERS Figure 1: Detailed Block Diagram of the ADuC844 -12- REV. PrB ...
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... By default the stack will operate exactly like an 8052 in that it will rollover from FFh to 00h in the general purpose RAM. On the ADuC844 however it is possible (by setting CFG844.7) to enable the 11-bit extended stack pointer. In this case the stack will rollover from FFh in RAM to 0100h in XRAM. ...
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... DPH, DPL), although INC DPTR instructions will automatically carry over to DPP three independent 8-bit registers (DPP, DPH, DPL). The ADuC844 supports dual data pointers. Refer to the Dual Data Pointer section later in this datasheet. Stack Pointer (SP and SPH) The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the ‘ ...
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... XRAM will be mapped into the lower 2kBytes of the external address space. If this bit is clear then the internal XRAM will not be accessible and the external data memory will be mapped into the lower memory. (see figure 3) -15- ADuC844 AFhH 00H No 2kBytes of external data ...
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... PRELIMINARY TECHNICAL DATA ADuC844 COMPLETE SFR MAP Figure 5 below shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR locations. Unoccupied locations in the SFR address space are not implemented; i.e., no register exists at this location unoccupied location is read, an unspecified value is returned ...
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... ADuC834 but the standard 12-cycle 8052 core has been replaced with a 12.6MIPs single cycle core. Since the ADuC844 and ADuC834 share the same feature set only the differences between the two chips are documented here. For full documentation on the ADuC834 please consult the datasheet available at http://www ...
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... PRELIMINARY TECHNICAL DATA ADuC844 Mnemonic Arithmetic LOGIC ANL A,Rn ANL A,@Ri ANL A,dir ANL A,#data ANL dir,A ANL dir,#data ORL A,Rn ORL A,@Ri ORL A,dir ORL A,#data ORL dir,A ORL dir,#data XRL A,Rn XRL A,@Ri XRL A,#data XRL dir,A XRL A,dir XRL dir,#data CLR A ...
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... Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Compare A, direct JNE relative Compare A, immediate JNE relative Compare register, immediate JNE relative Compare indirect, immediate JNE relative Decrement direct byte, JNZ relative No operation -19- ADuC844 Bytes Cycles ...
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... PRELIMINARY TECHNICAL DATA ADuC844 -20- REV. PrB ...