DS5001FP-12-44 Dallas Semiconducotr, DS5001FP-12-44 Datasheet - Page 4

• Manufacturer Part Number: DS5001FP-12-44
• Description: 128k Soft Microprocessor Chip
• Manufacturer: Dallas Semiconducotr

PIN DESCRIPTION
11, 9, 7,
5, 1, 79,
4, 6, 20,
80-PIN
MQFP
15, 17,
19, 21,
25, 27,
49, 50,
51, 56,
58, 60,
53, 16,
80, 76,
24, 26,
28, 30,
77, 75
29, 31
64, 66
47, 48
8, 18,
36
38
39
40
41
44
45
46
68
34
70
52
13
12
54
44-PIN
MQFP
41, 36,
42, 32,
30, 34,
35, 43,
1, 2, 3,
4, 5, 7,
(P0.5)
(P1.3)
14, 15
N/A
N/A
N/A
N/A
31
44
10
11
12
13
25
27
16
39
38
17
8
6
P3.2
P3.3
P0.0–P0.7
P1.0–P1.7
P2.0–P2.7
P3.0 RXD
P3.1 TXD
SIGNAL
P3.6
P3.7
XTAL2,
BA14–0
P3.4 T0
P3.5 T1
XTAL1
VCCO
GND
PSEN
VCC
RST
ALE
VLI
INT0
INT1
WR
RD
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires
external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in
this mode, it does not require pullups.
General-Purpose I/O Port 1
General-Purpose I/O Port 2. Also serves as the MSB of the address in expanded memory
accesses, and as pins of the RPC mode when used.
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on board
UART. This pin should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on board
UART. This pin should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0.
General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1.
General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input.
General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input.
General-Purpose I/O Port Pin. Also serves as the write strobe for expanded bus
operation.
General-Purpose I/O Port Pin. Also serves as the read strobe for expanded bus operation.
Program Store Enable. This active-low signal is used to enable an external program
memory when using the expanded bus. It is normally an output and should be unconnected
if not used.
down externally. This should only be done once the DS5001FP is already in a reset state.
The device that pulls down should be open drain since it must not interfere with
under normal operation.
Active-High Reset Input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally so this pin can be left unconnected if not used. An RC power-on
reset circuit is not needed and is not recommended.
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus
on port 0. This pin is normally connected to the clock input on a ’373 type transparent
latch.
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
Logic Ground
V
V
level of V
lithium cell remains isolated from a load. When V
V
Lithium Voltage Input. Connect to a lithium cell greater than V
V
Byte-Wide Address-Bus Bits 14–0. This bus is combined with the nonmultiplexed data
bus (BD7–0) to access NV SRAM. Decoding is performed using
Therefore, BA15 is not actually needed. Read/write access is controlled by R/
connect directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is used, BA13 and BA14 are
unconnected. If a 128k SRAM is used, the micro converts
CC
CCO
LI
LImax
source. V
- +5V
- V
as shown in the electrical specifications. Nominal value is +3V.
CC
CC
. When power is above the lithium input, power will be drawn from V
PSEN
Output. This is switched between V
CCO
should be connected to the V
also is used to invoke the bootstrap loader. At this time,
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DESCRIPTION
CC
CC
pin of an SRAM.
CC
and V
is below V
LI
CE2
by internal circuits based on the
LI
and
LIMIN
, the V
CE1
CE3
and no greater than
through
CCO
to serve as A16
PSEN
switches to the
W
DS5001FP
CE4
. BA14–0
PSEN
is pulled
CC
.
. The