PDI1394P21BE Philips Semiconductors, PDI1394P21BE Datasheet
PDI1394P21BE
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PDI1394P21BE Summary of contents
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PDI1394P21 3-port physical layer interface Objective specification hilips Semiconductors INTEGRATED CIRCUITS 1999 Jul 09 ...
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... Philips Semiconductors 3-port physical layer interface 1.0 FEATURES Fully supports provisions of IEEE 1394–1995 Standard for high performance serial bus and the P1394a supplement (Version 2.0) Full P1394a support includes: – Connection debounce – Arbitrated short reset – Multispeed concatenation – Arbitration acceleration – ...
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... Philips Semiconductors 3-port physical layer interface 4.0 PIN CONFIGURATION LREQ 1 SYSCLK 2 DGND 3 CTL0 4 CTL1 5 DVDD DGND 16 CNA LPS 19 DGND 5.0 PIN DESCRIPTION Name Pin Type Pin Numbers AGND Supply 36, 37, 38, 39, 40, ...
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... Philips Semiconductors 3-port physical layer interface Name Pin Type Pin Numbers C/LKON CMOS 5V tol 22 DGND Supply 3, 16, 20, 21, 28, 70, 80 D0–D7 CMOS 5V tol 7, 8, 10, 11, 12, 13, 14, 15 DVDD Supply 6, 29, 30, 68, 69, 79 /ISO CMOS 26 LPS CMOS 5V tol 19 LREQ CMOS 5V tol 1 NC ...
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... Philips Semiconductors 3-port physical layer interface Name Pin Type Pin Numbers /RESET CMOS 5V tol 78 R0, R1 Bias 66, 67 SYSCLK CMOS 2 TEST0 CMOS 33 TEST1 CMOS 32 TPA0+, Cable 45, 52, 58 TPA1+, TPA2+ TPA0–, Cable 44, 51, 57 TPA1–, TPA2– TPB0+, Cable 43, 50, 56 TPB1+, TPB2+ TPB0– ...
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... Philips Semiconductors 3-port physical layer interface 6.0 BLOCK DIAGRAM CPS LPS /ISO C/LKON SYSCLK LREQ CTL0 LINK CTL1 INTERFACE D0 I PC0 PC1 PC2 CNA R0 R1 TPBIAS0 TPBIAS1 TPBIAS2 PD /RESET 7.0 FUNCTIONAL SPECIFICATION The PDI1394P21 requires only an external 24.576 MHz crystal as a reference ...
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... Philips Semiconductors 3-port physical layer interface data bits are split into two-, four- or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports ...
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... Philips Semiconductors 3-port physical layer interface 8.0 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL SYMBOL PARAMETER PARAMETER V DC supply voltage input voltage I V –5V 5 volt tolerant input voltage range ...
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... Philips Semiconductors 3-port physical layer interface 10.0 CABLE DRIVER SYMBOL SYMBOL PARAMETER PARAMETER V Differential output voltage OD I Driver Difference current, TPA+, TPA–, TPB+, TPB– O(diff) I Common mode speed signaling current, TPB+, TPB– OFF state differential voltage OFF NOTES: 1. Limits defined as algebraic sum of TPA+ and TPA– ...
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... Philips Semiconductors 3-port physical layer interface 12.0 OTHER DEVICE I/O SYMBOL PARAMETER I I Supply current Supply current DD Supply current in power down or I DD–PD suspend mode V Cable power status threshold voltage High-level output voltage. pins CTLn CTL V OH Dn, SYSCLK, CNA, C/LKON ...
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... Philips Semiconductors 3-port physical layer interface 13.0 THERMAL CHARACTERISTICS SYMBOL SYMBOL PARAMETER PARAMETER R jA Junction-to-free-air thermal resistance 14.0 AC CHARACTERISTICS SYMBOL PARAMETER Transmit jitter Transmit skew t TPA, TPB differential output voltage rise time r t TPA, TPB differential output voltage fall time f t Setup time, CTL0, CTL1, D1–D7, LREQ to SYSCLK ...
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... Philips Semiconductors 3-port physical layer interface 16.0 INTERNAL REGISTER CONFIGURATION There are 16 accessible internal registers in the PDI1394P21. The configuration of the registers at addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected ...
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... Philips Semiconductors 3-port physical layer interface FIELD SIZE TYPE Pwr_Class 3 Rd/Wr Node power class. This field indicates this node’s power consumption and source characteristics and is replicated in the pwr field (bits 21–23) of the self-ID packet. This field is reset to the state specified by the PC0–PC2 input terminals upon hardware reset, and is unaffected by a bus reset. See Table 18. ...
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... Philips Semiconductors 3-port physical layer interface The Port Status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is shown in Table 3 and corresponding field descriptions given in Table 4 ...
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... Vendor_ID 24 Rd Manufacturer’s organizationally unique identifier (OUI). For the PDI1394P21, this field is 00_06_37h (Philips Semiconductors) (the MSB is at register address 1010b). Product_ID 24 Rd Product identifier. For the PDI1394P21, this field is 43_10_00h (the MSB is at register address 1101b). 1999 Jul 09 ...
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... Philips Semiconductors 3-port physical layer interface 17.0 APPLICATION INFORMATION PDI1394P21 CABLE PORT The IEEE Std 1394–1995 calls for a 250 pF capacitor, which is a non-standard component value. A 220 pF capacitor is recommended. Figure 4. Twisted pair cable interface connections CHASSIS GROUND 3 DGND 0.001 F 0 DVDD V DD Use one of these networks per side for all digital power and ground pins and one per side for all analog power and ground pins ...
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... Philips Semiconductors 3-port physical layer interface 17.1 External Component Connections 24.576 MHz 0 LREQ 2 SYSCLK 3 DGND 4 CTL0 5 CTL1 6 DVDD DGND 17 CNA CNA OUT 18 PD POWER DOWN LINK PULSE 19 LPS ...
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... Philips Semiconductors 3-port physical layer interface 17.2 Using the PDI1394P21 with a non-P1394a link layer The PDI1394P21 implements the PHY-LLC interface specified in the P1394a Supplement. This interface is based upon the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in older PHY devices. The PHY-LLC interface specified in P1394a is completely compatible with the older Annex J interface ...
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... PRINCIPLES OF OPERATION The PDI1394P21 is designed to operate with an LLC such as the Philips Semiconductors PDI1394L11 or PDI1394L21. The following paragraphs describe the operation of the PHY-LLC interface. The interface to the LLC consists of the SYSCLK, CTL0–CTL1, D0–D7, LREQ, LPS, C/LKON, and /ISO terminals on the PDI1394P21 as shown in Figure 9 ...
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... Philips Semiconductors 3-port physical layer interface LR0 LR1 18.1 LLC service request To request access to the bus, to read or write a PHY register control arbitration acceleration, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 10. The length of the stream will vary depending on the type of request as shown in Table 9 ...
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... Philips Semiconductors 3-port physical layer interface For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 14. Table 14. Write Register Request BIT(S) NAME DESCRIPTION 0 Start Bit Indicates the beginning of the transfer (always 1). 1–3 Request Type A 101 indicating that this is a write register request. 4– ...
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... Philips Semiconductors 3-port physical layer interface 18.2 Status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting Status (01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals ...
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... Philips Semiconductors 3-port physical layer interface 18.3 Receive Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting Receive on the CTL terminals and a logic 1 on each of the D terminals (“data-on” indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 17) on the D terminals, followed by packet data ...
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... Philips Semiconductors 3-port physical layer interface The sequence of events for a null packet reception is as follows: Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle ...
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... Philips Semiconductors 3-port physical layer interface 18.4 Transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the link by asserting the Grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by Idle for one clock cycle ...
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... Philips Semiconductors 3-port physical layer interface The sequence of events for a cancelled/null packet transmission is as follows: Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link. Optional Idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle is optional ...
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... Philips Semiconductors 3-port physical layer interface LQFP80: plastic low profile quad flat package; 80 leads; body 1.4 mm 1999 Jul 09 27 Objective specification PDI1394P21 SOT315-1 ...
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... Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no ...