PDI1394P25EC Philips Semiconductors, PDI1394P25EC Datasheet
PDI1394P25EC
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PDI1394P25EC Summary of contents
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PDI1394P25 1-port 400 Mbps physical layer interface Preliminary data Supersedes data of 2001 Jul 18 hilips Semiconductors INTEGRATED CIRCUITS 2001 Sep 06 ...
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... The PDI1394P25 is designed to interface with a Link Layer Controller (LLC), such as the PDI1394L40 or PDI1394L41. ORDER CODE 0 to +70 C PDI1394P25BD 0 to +70 C PDI1394P25EC 2 Preliminary data PDI1394P25 (PAP package) PKG. DWG. # SOT314-2 SOT534-1 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 4.0 PIN AND BALL CONFIGURATION 4.1 LQFP CONFIGURATION 64 LREQ 1 SYSCLK 2 CNA 3 CTL0 4 CTL1 LPS 2001 Sep PDI1394P25 18 19 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 4.2 LFBGA CONFIGURATION BOTTOM (BALL) VIEW Ball Signal Ball A1 AGND AGND C5 A6 TPBIAS0 C6 A7 TPB0– AGND C8 B1 AGND D1 B2 AGND TPA0 TPA0– ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 5.0 PIN DESCRIPTION Name Pin Type LQFP Pin Numbers Numbers AGND Supply 32, 33, 39, 48, 49 Supply 30, 31, DD 42, 51, 52 BRIDGE CMOS 28 C/LKON CMOS 5 V tol 19 CNA CMOS 3 CPS CMOS 24 CTL0, CMOS 5 V tol 4 CTL1 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface Name Pin Type LQFP Pin Numbers Numbers D0–D7 CMOS 5 V tol 10, 11, 12, 13 DGND Supply 17, 18, 63 Supply 25, 26, DD 61, 62 ISO CMOS 23 LPS CMOS 5 V tol 15 LREQ CMOS 5 V tol 1 NC ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface Name Pin Type LQFP Pin Numbers Numbers PLLGND Supply 57, 58 PLLV Supply 56 DD RESET CMOS 5 V tol 53 R0 Bias SYSCLK CMOS 2 TEST0 CMOS 29 TESTM CMOS 27 TPA0+ Cable 37 TPA0– Cable 36 TPB0+ Cable 35 TPB0– ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 6.0 BLOCK DIAGRAM LPS /ISO C/LKON SYSCLK LREQ CTL0 LINK CTL1 INTERFACE D0 I PC0 PC1 PC2 CNA R0 R1 TPBIAS0 TESTM PD /RESET 7.0 FUNCTIONAL SPECIFICATION The PDI1394P25 requires only an external 24.576 MHz crystal as a reference ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface data bits are split into two-, four- or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The LPS input is considered inactive if it remains low for more than 2.6 s and is considered active otherwise. When the PDI1394P25 detects that LPS is inactive, it will place the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 9.0 RECOMMENDED OPERATING CONDITIONS SYMBOL SYMBOL PARAMETER PARAMETER Supply voltage ly voltage DD DD High-level input voltage, LREQ CTL0, CTL1, D0-D7 V High-level input voltage, C/LKON IH PC0–PC2, ISO, PD RESET Low-level input voltage, LREQ, CTL0, CTL1, D0–D7 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 10.0 CABLE DRIVER SYMBOL SYMBOL PARAMETER PARAMETER V Differential output voltage OD I Driver Difference current, TPA+, TPA–, TPB+, TPB– O(diff) Common mode speed signaling output current, TPB TPB– V OFF state differential voltage ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 12.0 OTHER DEVICE I/O SYMBOL PARAMETER I Supply current DD I Supply current in power down mode DD–PD V Cable power status threshold voltage High-level output voltage, pins CTL0 CTL0 V OH CTL1, D0–D7, SYSCLK, CNA ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 13.0 THERMAL CHARACTERISTICS SYMBOL SYMBOL PARAMETER PARAMETER R jA Junction-to-free-air thermal resistance 14.0 AC CHARACTERISTICS SYMBOL PARAMETER Transmit jitter Transmit skew t TPA, TPB differential output voltage rise time r t TPA, TPB differential output voltage fall time ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 16.0 INTERNAL REGISTER CONFIGURATION There are 16 accessible internal registers in the PDI1394P25. The configuration of the registers at addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface FIELD SIZE TYPE LCtrl 1 Rd/Wr Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The Port Status page provides access to configuration and status information for each of a Phy’s ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is shown in Table 3 and corresponding field descriptions given in Table 4 ...
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... Vendor_ID 24 Rd Manufacturer’s organizationally unique identifier (OUI). For the PDI1394P25, this field is 00_60_37h (Philips Semiconductors) (the MSB is at register address 1010b). Product_ID 24 Rd Product identifier. For the PDI1394P25, this field is 41_28_01 (the MSB is at register address 1101b). The Vendor-Dependent page provides access to the special control features of the PDI1394P25, as well as configuration and status information used in manufacturing test and debug ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions FIELD SIZE TYPE Link_Speed 2 Rd/Wr Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows: This field is replicated in the “sp” field of the self-ID packet to indicate the speed capability of the node (PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs during self-ID ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 17.0 APPLICATION INFORMATION PDI1394P25 CABLE PORT The IEEE Std 1394–1995 calls for a 250 pF capacitor, which is a non-standard component value. A 220 pF capacitor is recommended. Figure 4. Twisted pair cable interface connections COMPLIANT DC-ISOLATED OUTER SHIELD TERMINATION ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface PHY 3.3 nF SQUARE WAVE SIGNAL 9.1 k Figure 8. Isolated circuit connection for LPS 2001 Sep 06 DD LINK LAYER CHIP LPS CONTENDER/ LINKON SV01807 LINK LAYER CHIP LINKON Figure 9. Three configurations for C/LKON signal ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 17.1 External Component Connections REFER TO SECTION 17 LREQ 2 SYSCLK CNA OUT 3 CNA 4 CTL0 5 CTL1 POWER DOWN LINK PULSE OR LPS LINK (REFER TO ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 17.2 RESET and Power Down Forcing the RESET pin low resets the internal logic to the Reset Start state and deactivates SYSCLK. Returning the RESET pin high causes a Bus Reset condition on the active cable ports. For ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface During bus initialization following a bus-reset, each PHY transmits a self-ID packet that indicates, among other information, the speed capability of the PHY. The bus manager (if one exists) may build a speed-map from the collected self-ID packets. This speed-map ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface introduced into the PHY’s Phase Lock Loop, and minimizing any emissions from the circuit. The crystal and two load capacitors should be considered as a unit during layout. The crystal and load capacitors should be placed as close as possible to one another while minimizing the loop area created by the combination of the three components ...
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... Mbps physical layer interface 18.0 PRINCIPLES OF OPERATION The PDI1394P25 is designed to operate with an LLC such as the Philips Semiconductors PDI1394L11 or PDI1394L21. The following paragraphs describe the operation of the PHY-LLC interface. The interface to the LLC consists of the SYSCLK, CTL0–CTL1, D0–D7, LREQ, LPS, C/LKON, and ISO terminals on the PDI1394P25 as shown in Figure 13 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface LR0 LR1 18.1 LLC service request To request access to the bus, to read or write a PHY register control arbitration acceleration, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 14. The length of the stream will vary depending on the type of request as shown in Table 11 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 16. Table 16. Write Register Request BIT(S) NAME DESCRIPTION 0 Start Bit Indicates the beginning of the transfer (always 1). 1–3 Request Type A 101 indicating that this is a write register request ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 18.2 Status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting Status (01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 18.3 Receive Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting Receive on the CTL terminals and a logic 1 on each of the D terminals (“data-on” indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 19) on the D terminals, followed by packet data ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The sequence of events for a null packet reception is as follows: Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 18.4 Transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the link by asserting the Grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by Idle for one clock cycle ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The sequence of events for a cancelled/null packet transmission is as follows: Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link. Optional Idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle is optional ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface Table 20. LPS Timing Parameters PARAMETER T LPS low time (when pulsed) (see Note 1) LPSL T LPS high time (when pulsed) (see Note 1) LPSH LPS duty cycle (when pulsed) (see Note 2) T Time for PHY to recognize LPS deasserted and reset the interface ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The sequence of events for resetting the PHY-LLC interface when the differentiated mode of operation (ISO terminal is low follows: 1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The sequence of events for resetting the PHY-LLC interface when the nondifferentiated mode of operation (ISO terminal is high follows: 1. Normal operation. Interface is operating normally, with LPS asserted, SYSCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The sequence of events for disabling the PHY-LLC interface when the differentiated mode of operation (ISO terminal is low follows: 1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The sequence of events for disabling the PHY-LLC interface when the non-differentiated mode of operation (ISO terminal is high follows: 1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface The sequence of events for initialization of the PHY-LLC interface when the interface is in the differentiated mode of operation (ISO terminal is low follows: 1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum T ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 19.0 POWER-CLASS PROGRAMMING The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 21. The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm 2001 Sep 06 41 Preliminary data PDI1394P25 SOT314-2 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls; body 1.05 mm 2001 Sep 06 42 Preliminary data PDI1394P25 SOT534-1 ...
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... Philips Semiconductors 1-port 400 Mbps physical layer interface 2001 Sep 06 NOTES 43 Preliminary data PDI1394P25 ...
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... Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. ...