ADG431 Analog Devices, ADG431 Datasheet - Page 6

• Manufacturer Part Number: ADG431
• Description: LC2MOS Precision Quad SPST Switches
• Manufacturer: Analog Devices

ADG431/ADG432/ADG433
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors from a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch up. With trench isolation, this diode is removed, the result
being a latch-up proof switch.
110
100
120
100
80
60
40
90
80
70
60
100
100
Figure 7. Off Isolation vs. Frequency
Figure 8. Crosstalk vs. Frequency
1k
1k
FREQUENCY – Hz
FREQUENCY – Hz
10k
10k
100k
100k
V
V
V
V
V
V
DD
SS
L
1M
DD
SS
L
1M
= +5V
= +5V
= –15V
= +15V
= –15V
= +15V
10M
10M
–6–
APPLICATION
Figure 10 illustrates a precise, fast sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
mode, SW1 is opened and the signal is held by the hold capaci-
tor C
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 30 V/ s.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
reduces the hold time glitch while optimizing the acquisition
time. Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the 10 V
input range. Both the acquisition and settling times are 850 ns.
V
IN
H
.
T
R
E
N
C
H
AD845
+15V
–15V
Figure 10. Fast, Accurate Sample-and-Hold
V
P
N
S
+
–
C
P-CHANNEL
and C
OUT
Figure 9. Trench Isolation
V
S
S
G
follows the input signal V
+15V
SW2
SW1
SUBSTRATE (BACKGATE)
C
. This compensation network also
BURIED OXIDE LAYER
ADG431
ADG432
ADG433
V
P
D
–15V
+
+5V
T
R
E
N
C
H
D
D
75
V
N
P
R
S
+
–
C
2200pF
2200pF
N-CHANNEL
C
1000pF
C
C
V
H
G
IN
. In the hold
AD711
+15V
–15V
V
N
D
+
REV. B
T
R
E
N
C
H
V
OUT