PEF2091 Siemens Semiconductor Group, PEF2091 Datasheet - Page 209

• Manufacturer Part Number: PEF2091
• Description: ICs for Communications(ISDN Echocancellation Circuit)
• Manufacturer: Siemens Semiconductor Group

5.1
The cause of an interrupt is determined by reading the Interrupt Status Register (ISTA).
In this register, 7 interrupt sources can be directly read. Interrupt bits are cleared by
reading the corresponding registers. ISTA:D is cleared after DRI and DRU have been
read. ISTA:B1 is cleared after RB1I and RB1U have been read. ISTA:B2 is cleared after
RB2I and RB2U have been read etc. ISTA:CICI is cleared after CIRI is read, ISTA:CICU
is cleared after CIRU is read. ISTA:SF indicates a superframe marker received from the
transceiver core. It is cleared when the ISTA register has been read. Pin INT is set to "0"
if one bit of ISTA changes from "0" to "1", except for the bit masked in the MASK register.
The MASK register allows to prevent an interrupt to influence the INT pin. Setting the bits
of MASK that correspond to the bits of ISTA to "1" masks the bits, i.e. the bits are still set
in ISTA, but they do not contribute to the input of the NOR-function on the interrupt bits
which sets the INT pin. The interrupt structure is illustrated in Figure 90:
Figure 90 Interrupt Structure
5.1.1
The Monitor Data Receive (MDR) and the Monitor End of Reception (MER) interrupt
status bits have two enable bits, Monitor Receive Interrupt Enable (MRE) and MR-bit
Control (MRC). The Monitor channel Data Acknowledged (MDA) and Monitor channel
Data Abort (MAB) interrupt status bits have a common enable bit Monitor Interrupt
Enable (MXE).
MRE prevents the occurrence of the MDR status, including when the first byte of a
packet is received. When MRE is active ("1") but MRC is inactive, the MDR interrupt
status is generated only for the first byte of a receive packet. When both MRE and MRC
are active, MDR is generated and all received Monitor bytes - marked by a low edge in
Semiconductor Group
Interrupt Structure
Monitor-Channel Interrupt Logic
D
CICI
CICU
SF
MDR
B1
B2
MDA
MASK
INT
D
CICI
CICU
SF
MDR
B1
B2
MDA
ISTA
209
MOSR
MDR
MER
MDA
MAB
MAC
Register Description
MOCR
MRE
MRC
MXE
MXC
ITD08114
Data Sheet 01.99
PEB 2091
PEF 2091