SAF-C505-2RM Siemens Semiconductor Group, SAF-C505-2RM Datasheet - Page 61
![no-image](/images/manufacturer_photos/0/6/607/siemens_semiconductor_group_sml.jpg)
SAF-C505-2RM
Manufacturer Part Number
SAF-C505-2RM
Description
8-Bit CMOS Microcontroller
Manufacturer
Siemens Semiconductor Group
Datasheet
1.SAF-C505-2RM.pdf
(85 pages)
- Current page: 61 of 85
- Download datasheet (336Kb)
Notes:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the
2) Capacitive loading on ports 0 and 2 may cause the
3) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin
4) Not 100% tested, guaranteed by design characterization.
5) Only valid for C505A and C505CA.
6) Only valid for C505A and C505CA in programming mode.
7)
8)
9)
10)
11)
12) The typical
13) The maximum
Semiconductor Group
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
0.9
exceeds the specified range (i.e.
remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.
I
XTAL1 driven with
EA = Port 0 = RESET =
I
XTAL1 driven with
RESET = EA =
I
I
I
EA = Port 0 =
all other pins are disconnected.
CC
CC
CC
CC
PD
V
(power-down mode) is measured under following conditions:
(active mode) is measured with:
(idle mode) is measured with all output pins disconnected and with all peripherals disabled;
(active mode with slow-down mode) is measured : TBD
(idle mode with slow-down mode) is measured : TBD
CC
specification when the address lines are stabilizing.
I
CC
V
I
values are periodically measured at
CC
V
CC
SS
; RESET =
values are measured under worst case conditions (
t
t
R
R
; Port0 =
,
,
t
t
F
F
V
= 5 ns, 50% duty cycle ,
= 5 ns, 50% duty cycle,
CC
; all other pins are disconnected.
V
V
CC
SS
V
OV
; all other pins are disconnected;
; XTAL2 = N.C.; XTAL1 =
>
V
CC
+ 0.5 V or
V
V
IL
61
IL
T
V
=
=
A
V
OV
V
OH
= + 25 C but not 100% tested.
V
SS
SS
<
on ALE and PSEN to momentarily fall below the
V
+ 0.5 V,
+ 0.5 V,
SS
V
SS
- 0.5 V). The supply voltage
;
V
AGND
V
V
IH
IH
T
=
=
A
=
V
= 0 C or – 40 C and
V
V
CC
CC
SS
– 0.5 V; XTAL2 = N.C.;
– 0.5 V; XTAL2 = N.C.;
;
V
AREF
C505A / C505CA
=
V
C505 / C505C
CC
V
CC
;
1997-12-01
and
V
V
CC
OL
V
= 5.5 V)
SS
of ALE
must
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