LX1710-1 Microsemi Corporation, LX1710-1 Datasheet - Page 14

• Manufacturer Part Number: LX1710-1
• Description: EVALUATION KIT
• Manufacturer: Microsemi Corporation

LXE1710 E
G
Series resistors (R6, R10, R11, R12) can be added to
the gate of MOSFETs (Q1 to Q4) to control the
switching transition times.
distortion as seen in the THD+N vs. Output Power
graph below.
however, increase power dissipation and therefore
slightly decrease the overall efficiency of the amplifier.
resistors, which improves (decreases) the THD+N
from 0.1% to 0.05% with a slight impact on efficiency
of approximately 2%. The recommended gate resistor
The oscillator is programmed by the external timing
components RPWM and CPWM.
frequency of 333kHz, RPWM and CPWM should be
set to 49.9kOhms and 100pF respectively. Note that
in order to keep the slope of the PWM ramp voltage
proportional to the supply voltage, both the ramp peak
Copyright
Rev. 1.1, 2000-12-01
ATE
O
SCILLATOR
0.26978
0.04675
R
0.005
0.001
ESISTOR
0.01
100
0.1
50
20
10
2
1
2000
50m
P+
N+
C
ONFIGURATION
VALUATION
The slower switching speeds will
10
10
R12
R11
100m
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: [phone]
V
IN
Q2
Q1
This reduces signal
200m
B
OARD
OUT+
For a nominal
V
IN
Linfinity Microelectronics Division
Gate Resistor Impact On THD+N
= 15V
500m
Microsemi
O utput P ower (W )
f
1
1.131
IN
= 1kHz
and valley voltages, and the charge and discharge
currents are proportional to the supply voltage. This
keeps the frequency relatively constant while keeping
the slope of the PWM ramp proportional to the voltage
on the VDD pin. For operating frequencies other than
333kHz, the frequency can be approximated by the
following equation:
For applications that require more than a single
channel, the oscillators of multiple LX1710/1711
controllers
operation. One unit, the master, is programmed for
the desired frequency with the RPWM and CPWM as
usual. Additional units will be slave units, and their
oscillators will be disabled by leaving the RPWM pin
disconnected. The CLOCK pin and the CPWM pin of
the slave units should be tied to the CLOCK pin and
the CPWM pin of the master unit respectively. In this
configuration, the CLOCK pins of the slave units begin
receiving instead of transmitting clock pulses. Also,
the CPWM pins quit driving the PWM capacitor in the
slave units. Note that for optimum performance, all
slave units should be located within a few inches of the
master unit.
M
S
YNCHRONIZATION
ULTI
Frequency
W ith 10
No Gate Resistor
2
C
HANNEL
can
R
L
Gate Resistor


(
be
. 0
5
R
577
EQUIREMENTS
configured
)(
R
PWM
10
)(
1
U
C
PWM
SER
for
AND
)
20
synchronous
G
F
24.56
320
REQUENCY
UIDE
Page 14
30
ns