EL5283C Elantec Semiconductor, EL5283C Datasheet - Page 7

• Manufacturer Part Number: EL5283C
• Description: Dual and Window 8ns High-Speed Comparators
• Manufacturer: Elantec Semiconductor

Pin Descriptions
Applications Information
Power Supplies and Circuit Layout
The EL5283C comparator operates with single and dual
supply with 5V to 12V between V
put side of the comparators is supplied by a single
supply from 2.7V to 5V. The rail to rail output swing
enables direct connection of the comparator to both
CMOS and TTL logic circuits. As with many high speed
devices, the supplies must be well bypassed. Elantec rec-
ommends a 4.7µF tantalum in parallel with a 0.1µF
ceramic. These should be placed as close as possible to
the supply pins. Keep all leads short to reduce stray
capacitance and lead inductance. This will also mini-
m i z e u n w a n t e d p a r a s i t i c f e e d b a c k a r o u n d t h e
comparator. The device should be soldered directly to
the PC board instead of using a socket. Use a PC board
with a good, unbroken low inductance ground plane.
Good ground plane construction techniques enhance sta-
bility of the comparators.
Pin Number
10
1
2
3
4
5
6
7
8
9
Pin Name
VREFH
LATCH
VREFL
OUTH
OUTL
GDN
VSD
VS+
VS-
IN
Positive supply voltage
Upper voltage reference
Input
Lower voltage reference
Negative supply voltage
Digital ground
Low output
Latch
High output
Digital supply voltage
S
+ and V
Function
S
-. The out-
Dual and Window 8ns High-Speed Comparators
7
Input Voltage Considerations
The EL5283C input range is specified from 0.1V below
V
limit is that the output still responds correctly to a small
differential input signal. The differential input stage is a
pair of PNP transistors, therefore, the input bias current
flows out of the device. When either input signal falls
below the negative input voltage limit, the parasitic PN
junction formed by the substrate and the base of the PNP
will turn on, resulting in a significant increase of input
bias current. If one of the inputs goes above the positive
input voltage limit, the output will still maintain the cor-
rect logic level as long as the other input stays within the
input range. However, the propagation delay will
increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differ-
ential voltages greater than the supply voltage should be
avoided to prevent damages to the input stage. Inputs of
unused channels should not be left floating. They should
be driven to a known state. For example, one input can
S
EL5283C - Preliminary
- to 2.25V below V
(Reference Circuit 4)
(Reference Circuit 4)
(Reference Circuit 2)
(Reference Circuit 3)
(Reference Circuit 2)
VREF
Equivalent Circuit
S
+. The criterion for the input
Circuit 4
V
V
S
S
IN
+
-