LP2996LQ National Semiconductor, LP2996LQ Datasheet - Page 10

• Manufacturer Part Number: LP2996LQ
• Description: DDR Termination Regulator
• Manufacturer: National Semiconductor

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Component Selections
OUTPUT CAPACITOR
The LP2996 has been designed to be insensitive of output
capacitor size or ESR (Equivalent Series Resistance). This
allows the flexibility to use any capacitor desired. The choice
for output capacitor will be determined solely on the applica-
tion and the requirements for load transient response of V
As a general recommendation the output capacitor should
be sized above 100 µF with a low ESR for SSTL applications
with DDR-SDRAM. The value of ESR should be determined
by the maximum current spikes expected and the extent at
which the output voltage is allowed to droop. Several capaci-
tor options are available on the market and a few of these
are highlighted below:
AL - It should be noted that many aluminum electrolytics only
specify impedance at a frequency of 120 Hz, which indicates
they have poor high frequency performance. Only aluminum
electrolytics that have an impedance specified at a higher
frequency (between 20 kHz and 100 kHz) should be used for
the LP2996. To improve the ESR several AL electrolytics can
be combined in parallel for an overall reduction. An important
note to be aware of is the extent at which the ESR will
change over temperature. Aluminum electrolytic capacitors
can have their ESR rapidly increase at cold temperatures.
Ceramic - Ceramic capacitors typically have a low capaci-
tance, in the range of 10 to 100 µF range, but they have
excellent AC performance for bypassing noise because of
very low ESR (typically less than 10 mΩ). However, some
dielectric types do not have good capacitance characteris-
tics as a function of voltage and temperature. Because of the
typically low value of capacitance it is recommended to use
ceramic capacitors in parallel with another capacitor such as
an aluminum electrolytic. A dielectric of X5R or better is
recommended for all ceramic capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP
are available from several manufacturers. These offer a
large capacitance while maintaining a low ESR. These are
the best solution when size and performance are critical,
although their cost is typically higher than any other capaci-
tor.
Thermal Dissipation
Since the LP2996 is a linear regulator any current flow from
V
To prevent damaging the part from exceeding the maximum
allowable junction temperature, care should be taken to
derate the part dependent on the maximum expected ambi-
ent temperature and power dissipation. The maximum allow-
able internal temperature rise (T
given the maximum ambient temperature (T
application and the maximum allowable junction temperature
(T
From this equation, the maximum power dissipation (P
of the part can be calculated:
The θ
ables: the package used; the thickness of copper; the num-
ber of vias and the airflow. For instance, the θ
is 163˚C/W with the package mounted to a standard 8x4
2-layer board with 1oz. copper, no airflow, and 0.5W dissi-
pation at room temperature. This value can be reduced to
TT
Jmax
will result in internal power dissipation generating heat.
JA
).
of the LP2996 will be dependent on several vari-
T
Rmax
P
Dmax
= T
= T
Jmax
Rmax
− T
Rmax
/ θ
Amax
JA
) can be calculated
(Continued)
JA
Amax
of the SO-8
) of the
Dmax
TT
.
)
10
151.2˚C/W by changing to a 3x4 board with 2 oz. copper that
is the JEDEC standard. Figure 2 shows how the θ
with airflow for the two boards mentioned.
Additional improvements can be made by the judicious use
of vias to connect the part and dissipate heat to an internal
ground plane. Using larger traces and more copper on the
top side of the board can also help. With careful layout it is
possible to reduce the θ
shown in Figure 2
Layout is also extremely critical to maximize the output
current with the LLP package. By simply placing vias under
the DAP the θ
the LLP thermal data when placed on a 4-layer JEDEC
board with copper thickness of 0.5/1/1/0.5 oz. The number of
vias, with a pitch of 1.27 mm, has been increased to the
maximum of 4 where a θ
Via wall thickness for this calculation is 0.036 mm for 1oz.
Copper.
FIGURE 3. LLP-16 θ
FIGURE 2. θ
JA
can be lowered significantly. Figure 3 shows
JA
JA
JA
JA
Board))
vs # of Vias (4 Layer JEDEC
further than the nominal values
of 50.41˚C/W can be obtained.
vs Airflow (SO-8)
20057508
20057507
JA
varies