LP2997MX National Semiconductor, LP2997MX Datasheet - Page 10

• Manufacturer Part Number: LP2997MX
• Description: DDR-II Termination Regulator
• Manufacturer: National Semiconductor

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Typical Application Circuits
Several different application circuits have been shown to
illustrate some of the options that are possible in configuring
the LP2997. Graphs of the individual circuit performance can
be found in the Typical Performance Characteristics section
in the beginning of the datasheet. These curves illustrate
how the maximum output current is affected by changes in
AVIN and PVIN.
This circuit permits termination in a minimum amount of
board space and component count. Capacitor selection can
be varied depending on the number of lines terminated and
the maximum load transient. However, with motherboards
and other applications where V
plane it is advisable to use multiple bulk capacitors and
addition to high frequency decoupling. The bulk output ca-
pacitors should be situated at both ends of the V
optimal placement. Large aluminum electrolytic capacitors
are used for their low ESR and low cost.
PCB Layout Considerations
1.
2. V
as close as possible to the PVIN pin.
at the point where regulation is required. For mother-
board applications an ideal location would be at the
center of the termination bus.
The input capacitor for the power rail should be placed
SENSE
should be connected to the V
TT
is distributed across a long
FIGURE 2. Recommended DDR-II Termination
TT
termination bus
TT
plane for
10
Figure 2 shows the recommended circuit configuration for
DDR-II applications. The output stage is connected to the
1.8V rail and the AVIN pin can be connected to either a 2.5V,
3.3V or 5V rail.
3. V
4. For improved thermal performance excessive top side
5. Care should be taken when routing the V
6. V
at either the DIMM or the Chipset. This provides the
most accurate point for creating the reference voltage.
copper should be used to dissipate heat from the pack-
age. Numerous vias from the ground connection to the
internal ground plane will help. Additionally these can be
located underneath the package if manufacturing stan-
dards permit.
avoid noise pickup from switching I/O signals. A 0.1uF
ceramic capacitor located close to the
used to filter any unwanted high frequency signal. This
can be an issue especially if long
ceramic capacitor for improved performance. This ca-
pacitor should be located as close as possible to the
V
DDQ
REF
REF
pin.
can be connected remotely to the V
should be bypassed with a 0.01 µF or 0.1 µF
20109413
SENSE
SENSE
traces are used.
SENSE
DDQ
can also be
rail input
trace to