24LC16 MicrochipTechnology, 24LC16 Datasheet - Page 5

• Manufacturer Part Number: 24LC16
• Description: 16K2.5VI2COSerialEEPROM
• Manufacturer: MicrochipTechnology

3.6
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code, for the 24LC16B this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the block select
bits (B2, B1, B0). They are used by the master device
to select which of the eight 256 word blocks of memory
are to be accessed. These bits are in effect the three
most significant bits of the word address. It should be
noted that the protocol limits the size of the memory to
eight blocks of 256 words, therefore the protocol can
support only one 24LC16B per system.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC16B monitors the
SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24LC16B will select a read
or write operation.
FIGURE 3-2:
FIGURE 4-1:
FIGURE 4-2:
SDA LINE
BUS ACTIVITY
MASTER
Operation
BUS ACTIVITY
SDA LINE
1996 Microchip Technology Inc.
BUS ACTIVITY
MASTER
BUS ACTIVITY
X = Don’t care
Read
Write
1
START
Device Addressing
0
Control
SLAVE ADDRESS
Code
1010
1010
CONTROL BYTE
ALLOCATION
BYTE WRITE
PAGE WRITE
1
S
S
T
A
R
T
S
S
T
A
R
T
0
CONTROL
Block Address
Block Address
Block Select
CONTROL
BYTE
X
BYTE
READ/WRITE
X
A
C
K
R/W
X
ADDRESS (n)
R/W
WORD
A
1
0
A
C
K
A
C
K
ADDRESS
WORD
4.0
4.1
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24LC16B. After receiving
another acknowledge signal from the 24LC16B the
master device will transmit the data word to be written
into the addressed memory location. The 24LC16B
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24LC16B will not generate acknowl-
edge signals (Figure 4-1).
4.2
The write control byte, word address and the first data
byte are transmitted to the 24LC16B in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to 16 data bytes to the
24LC16B which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
DATA n
WRITE OPERATION
Byte Write
Page Write
A
C
K
A
C
K
DATA n + 1
DATA
24LC16B
A
C
K
DATA n + 15
DS20070G-page 5
A
C
K
P
S
T
O
P
A
C
K
S
T
O
P
P