24C02C-EP MicrochipTechnology, 24C02C-EP Datasheet - Page 7

• Manufacturer Part Number: 24C02C-EP
• Description: 2K5.0VI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

6.0
6.1
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24C02C. After
receiving another acknowledge signal from the
24C02C the master device will transmit the data word
to be written into the addressed memory location. The
24C02C acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle, and during this time the 24C02C will not generate
acknowledge signals (Figure 6-1). If an attempt is made
to write to the protected portion of the array when the
hardware write protection has been enabled, the device
will acknowledge the command but no data will be writ-
ten. The write cycle time must be observed even if the
write protection is enabled.
FIGURE 6-1:
FIGURE 6-2:
SDA LINE
BUS ACTIVITY
MASTER
BUS ACTIVITY
SDA LINE
1997 Microchip Technology Inc.
BUS ACTIVITY
MASTER
BUS ACTIVITY
WRITE OPERATIONS
Byte Write
S
S
T
A
R
T
BYTE WRITE
PAGE WRITE
S
T
A
R
T
S
CONTROL
BYTE
CONTROL
BYTE
A
C
K
ADDRESS (n)
WORD
A
C
K
Preliminary
A
C
K
ADDRESS
WORD
DATA n
6.2
The write control byte, word address and the first data
byte are transmitted to the 24C02C in the same way as
in a byte write. But instead of generating a stop condi-
tion, the master transmits up to 15 additional data bytes
to the 24C02C which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order four bits of the word address remains con-
stant. If the master should transmit more than 16 bytes
prior to generating the stop condition, the address
counter will roll over and the previously received data
will be overwritten. As with the byte write operation,
once the stop condition is received an internal write
cycle will begin (Figure 6-2). If an attempt is made to
write to the protected portion of the array when the
hardware write protection has been enabled, the device
will acknowledge the command but no data will be writ-
ten. The write cycle time must be observed even if the
write protection is enabled.
6.3
The WP pin must be tied to V
the upper half of the array (080-0FF) will be write pro-
tected. If the WP pin is tied to V
to all address locations are allowed.
Page Write
WRITE PROTECTION
A
C
K
A
C
K
DATA n +1
DATA
A
C
K
CC
SS
, then write operations
or V
24C02C
DATA n + 15
SS
DS21202A-page 7
. If tied to V
A
C
K
P
S
T
O
P
A
C
K
S
T
O
P
P
CC
,