93LC86-P Microchip Technology, 93LC86-P Datasheet - Page 2

• Manufacturer Part Number: 93LC86-P
• Description: 8K/16K 2.5V Microwire Serial EEPROM
• Manufacturer: Microchip Technology

www.fairchildsemi.com
Functional Description
The DM96LS02 dual retriggerable resettable monostable
multivibrator has two DC coupled trigger inputs per func-
tion, one active LOW (I0) and one active HIGH (I1). The I1
input and I0 input of the DM96LS02 utilize an internal
Schmitt trigger with hysteresis of 0.3V to provide increased
noise immunity. The use of active HIGH and LOW inputs
allows either rising or falling edge triggering and optional
non-retriggerable operation. The inputs are DC coupled
making triggering independent of input transition times.
When input conditions for triggering are met, the Q output
goes HIGH and the external capacitor is rapidly discharged
and then allowed to recharge. An input trigger which occurs
Logic Diagram
Operation Notes
TIMING
1. An external resistor (R
are required as shown in the Logic Diagram. The value of
R
2. The value of C
available. If, however, the capacitor has significant leakage
relative to V
the pulse width obtained.
3. The output pulse width t
1000 pF is determined as follows:
Where R
is in F, t is in ms.
4. The output pulse width for R
should be determined from pulse width versus C
graphs.
5. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
6. Under any operating condition, C
kept as close to the circuit as possible to minimize stray
capacitance and reduce noise pickup.
7. V
quency standards so that switching transients on V
ground leads do not cause interaction between one shots.
Use of a 0.01 F to 0.1 F bypass capacitor between V
and ground located near the circuit is recommended.
X
may vary from 1.0 k
CC
t
W
and ground wiring should conform to good high fre-
X
0.43 R
is in k , C
CC
/R
X
X
X
C
X
may vary from 0 to any necessary value
the timing equations may not represent
X
is in pF, t is in ns or R
X
to 1.0 M .
) and an external capacitor (C
W
for R
X
10 k
X
X
and R
10 k
or C
X
(Min) must be
X
X
is in k , C
and C
1000 pF
X
CC
or R
and
X
CC
X
X
X
)
2
during the timing cycle will retrigger the circuit and result in
Q remaining HIGH. The output pulse may be terminated (Q
to the LOW state) at any time by setting the Direct Clear
input LOW. Retriggering may be inhibited by tying the Q
output to I0 or the Q output to I1. Differential sensing tech-
niques are used to obtain excellent stability over tempera-
ture and power supply variations and a feedback
Darlington capacitor discharge circuit minimizes pulse
width variation from unit to unit. Schottky TTL output stages
provide high switching speeds and output compatibility with
all TTL logic families.
TRIGGERING
1. The minimum negative pulse width into I0 is 8.0 ns; the
minimum positive pulse width into I1 is 12 ns.
2. Input signals to the DM96LS02 exhibiting slow or noisy
transitions can use either trigger as both are Schmitt trig-
gers.
3. When non-retriggerable operation is required, i.e., when
input triggers are to be ignored during quasi-stable state,
input latching is used to inhibit retriggering.
4. An overriding active LOW level direct clear is provided
on each multivibrator. By applying a LOW to the clear, any
timing cycle can be terminated or any new cycle inhibited
until the LOW reset input is removed. Trigger inputs will not
produce spikes in the output when the reset is held LOW. A
LOW-to-HIGH transition on C
DM96LS02. If the C
trigger transition, the circuit will respond to the trigger.
D
input goes HIGH coincident with a
D
will not trigger the