CY62256V Cypress Semiconductor, CY62256V Datasheet - Page 5

• Manufacturer Part Number: CY62256V
• Description: 32K x 8 Static RAM
• Manufacturer: Cypress Semiconductor

Switching Characteristics
Switching Waveforms
Read Cycle No. 1
Read Cycle No. 2
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Shaded area contains advanced information.
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
Notes:
10. Device is continuously selected. OE, CE = V
12. Address valid prior to or coincident with CE transition LOW.
11. WE is HIGH for read cycle.
8.
9.
DATA OUT
DATA OUT
CURRENT
ADDRESS
Parameter
SUPPLY
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
V
CE
OE
CC
[8,9]
[10, 11]
[11, 12]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
PREVIOUS DATA VALID
HIGH IMPEDANCE
t
PU
t
LZCE
Over the Operating Range
t
t
ACE
LZOE
PRELIMINARY
IL
.
Description
[6, 7]
[6]
t
OHA
50%
t
DOE
t
AA
[10, 11]
[10, 11]
t
RC
[5]
(continued)
5
t
RC
HZWE
Min.
DATA VALID
and t
CY62256V-55
55
45
45
40
25
0
0
0
3
SD
.
Max.
20
DATA VALID
Min.
CY62256V-70
70
60
60
50
30
0
0
0
3
t
t
HZOE
HZCE
t
PD
50%
Max.
CY62256V
25
IMPEDANCE
HIGH
C62256V–8
C62256V–9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ICC
ISB