LH28F800BG Sharp Electrionic Components, LH28F800BG Datasheet - Page 5

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LH28F800BG

Manufacturer Part Number
LH28F800BG
Description
8 M-bit (512 kB x 16) SmartVoltage Flash Memory
Manufacturer
Sharp Electrionic Components
Datasheet

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1 INTRODUCTION
This datasheet contains LH28F800BG-L speci-
fications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800BG-L
flash memory documentation also includes ordering
information which is referenced in Section 7.
1.1 New Features
Key enhancements of LH28F800BG-L SmartVoltage
flash memory are :
Note following important differences :
1.2 Product Overview
The LH28F800BG-L is a high-performance 8 M-bit
SmartVoltage flash memory organized as 512 k-
word of 16 bits. The 512 k-word of data is arranged
in two 4 k-word boot blocks, six 4 k-word parameter
blocks and fifteen 32 k-word main blocks which are
individually erasable in-system. The memory map is
shown in Fig. 1.
SmartVoltage technology provides a choice of V
and V
meet system performance and power expectations.
2.7 V V
power of 5 V V
approximately one-fourth the power of 5 V V
But, 5 V V
• SmartVoltage Technology
• Enhanced Suspend Capabilities
• Boot Block Architecture
• V
• To take advantage of SmartVoltage technology,
2.7 V, 3.3 V and 5 V block erase and word
write operations. Designs that switch V
during read operations should make sure that
the V
allow V
PPLK
PP
CC
PP
combinations, as shown in Table 1, to
has been lowered to 1.5 V to support
PP
consumes approximately one-fifth the
voltage transitions to GND.
connection to 2.7 V, 3.3 V or 5 V.
CC
CC
provides the highest read
and 3.3 V V
CC
consumes
PP
CC
off
CC
.
- 5 -
performance. V
eliminates the need for a separate 12 V converter,
while V
write performance. In addition to flexible erase and
program voltages, the dedicated V
complete data protection when V
Internal V
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.
A block erase operation erases one of the device’s
32 k-word blocks typically within 0.39 second (5 V
V
0.25 second (5 V V
other blocks. Each block can be independently
erased 100 000 times. Block erase suspend mode
allows system software to suspend block erase to
read data from, or write data to any other block.
Writing memory data is performed in word increments
of the device’s 32 k-word blocks typically within 8.4 µs
(5 V V
17 µs (5 V V
mode enables the system to read data from, or write
data to any other flash memory array location.
CC
Table 1 V
, 12 V V
V
CC
PP =
CC
, 12 V V
VOLTAGE
2.7 V
3.3 V
CC
5 V
Offered by SmartVoltage Technology
12 V maximizes block erase and word
PP
CC
CC
and V
), 4 k-word blocks typically within
, 12 V V
PP
PP
and V
), 4 k-word blocks typically within
LH28F800BG-L (FOR SOP)
CC
at 2.7 V, 3.3 V and 5 V
PP
PP
, 12 V V
detection circuitry auto-
PP
Voltage Combinations
2.7 V, 3.3 V, 5 V, 12 V
). Word write suspend
3.3 V, 5 V, 12 V
V
PP
PP
PP
5 V, 12 V
) independent of
≤ V
VOLTAGE
PP
PPLK
pin gives
.

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