HM62V16256C Hitachi Semiconductor, HM62V16256C Datasheet

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HM62V16256C

Manufacturer Part Number
HM62V16256C
Description
4 M SRAM (256-kword x 16-bit)
Manufacturer
Hitachi Semiconductor
Datasheet

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Description
The Hitachi HM62V16256C Series is 4-Mbit static RAM organized 262,144-word
Series has realized higher density, higher performance and low power consumption by employing CMOS
process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is
suitable for battery backup systems. It is packaged in standard 44-pin plastic TSOPII.
Features
• Completely static memory.
• Equal access and cycle times
• Common data input and output.
• Battery backup operation.
Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
Fast access time: 55 ns/70 ns (max)
Power dissipation:
Active: 5.0 mW/MHz (typ)(V
Standby: 2 µW (typ) (V
No clock or timing strobe required
Three state output
2 chip selection for battery backup
: 6.0 mW/MHz (typ) (V
: 2.4 µW (typ) (V
HM62V16256C Series
4 M SRAM (256-kword
CC
CC
= 2.5 V)
= 3.0 V)
CC
CC
= 2.5 V)
= 3.0 V)
16-bit)
ADE-203-1099D (Z)
16-bit. HM62V16256C
Jan. 31, 2001
Rev. 1.0

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HM62V16256C Summary of contents

Page 1

... HM62V16256C Series 4 M SRAM (256-kword Description The Hitachi HM62V16256C Series is 4-Mbit static RAM organized 262,144-word Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore suitable for battery backup systems ...

Page 2

... HM62V16256C Series Ordering Information Type No. Access time HM62V16256CLTT HM62V16256CLTT HM62V16256CLTT-5SL 55 ns HM62V16256CLTT-7SL Package 400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DB) ...

Page 3

... CS1 I/O0 38 I/O15 8 37 I/O1 I/O14 9 36 I/O13 I/ I/O12 I/ I/O11 I/ I/O5 I/O10 15 30 I/O6 I/ I/O8 I/ CS2 A17 A16 20 25 A15 A10 21 24 A14 A11 22 23 A12 A13 (Top view) HM62V16256C Series 3 ...

Page 4

... HM62V16256C Series Block Diagram LSB A12 A11 A10 A9 A8 A13 A14 A15 A16 A17 MSB A7 I/O0 I/O15 CS2 CS1 • • • Memory matrix Row • • 2,048 x 2,048 decoder • Column I/O • Input Column decoder data control LSB • ...

Page 5

... 2.0 — IH 2.0 — IH –0.2 — IL –0.3 — –20 — 30 ns. HM62V16256C Series Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable Value Unit –0 4 –0. 0.3* ...

Page 6

... HM62V16256C Series DC Characteristics Parameter Input leakage current Output leakage current Operating current Average HM62V16256C-5 I operating current HM62V16256C-7 I Standby current Standby current Output high voltage Output low voltage ...

Page 7

... Capacitance ( 1.0 MHz) Parameter Symbol Input capacitance Cin Input/output capacitance C I/O Note: 1. This parameter is sampled and not 100% tested. Min Typ Max Unit — — — — HM62V16256C Series Test conditions Note Vin = I/O 7 ...

Page 8

... Input rise and fall time • Input timing reference levels: 1 • Output timing reference levels: 1 • Input timing reference levels: 1 • Output timing reference levels: 1.4 V (HM62V16256C–5, V • Output load: See figures (Including scope and jig Dout ...

Page 9

... Output enable to output valid Output hold from address change LB, UB access time Chip select to output in low-Z LB, UB enable to low-z Output enable to output in low-Z Chip deselect to output in high-Z LB, UB disable to high-Z Output disable to output in high-Z HM62V16256C Series HM62V16256C -5 -7 Symbol Min Max Min t 55 — ...

Page 10

... HM62V16256C Series Write Cycle Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB, UB valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write ...

Page 11

... Read Cycle Address CS1 CS2 LB High impedance Dout t RC Valid address ACS1 CLZ1 t ACS2 CLZ2 BLZ OLZ HM62V16256C Series CHZ1 CHZ2 BHZ OHZ t OH Valid data 11 ...

Page 12

... HM62V16256C Series Write Cycle (1) (WE Clock) Address CS1 CS2 LB Din Dout Valid address WHZ * Valid data High impedance ...

Page 13

... Write Cycle (2) (CS Clock Address CS1 CS2 LB Din Dout ) Valid address High impedance HM62V16256C Series Valid data 13 ...

Page 14

... HM62V16256C Series Write Cycle (3) (LB, UB Clock Address CS1 CS2 LB Din Dout Valid address High impedance Valid data ...

Page 15

... Max 2.0 — 3 — 0 — 0 — — — — 3 +25˚C and not guaranteed. CC HM62V16256C Series 3 Unit Test conditions* V Vin 0V ( CS2 0 (2) CS2 V – 0 CS1 V – – 0 CS2 V – 0 CS1 0 ...

Page 16

... HM62V16256C Series Low V Data Retention Timing Waveform (1) (CS1 Controlled CDR 2.0 V CS1 0 V Low V Data Retention Timing Waveform (2) (CS2 Controlled CDR V CC 2.2 V CS2 Data Retention Timing Waveform (3) (LB, UB Controlled) Low CDR 2.0 V LB, UB ...

Page 17

... Package Dimensions HM62V16256CLTT Series (TTP-44DB) 18.41 18.81 Max 44 1 0.80 *0.30 0.10 0.13 0.25 0.05 1.005 Max 0.10 *Dimension including the plating thickness Base material dimension 11.76 Hitachi Code JEDEC EIAJ Mass (reference value) HM62V16256C Series 0.80 0.20 0 – 5 0.50 0.10 TTP-44DB — — 0.43 g Unit ...

Page 18

... HM62V16256C Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...

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