NCP1031 ON, NCP1031 Datasheet - Page 14

• Manufacturer Part Number: NCP1031
• Description: Low Power PWM Controller with On-Chip Power Switch and Startup Circuits for 48V Telecom Systems
• Manufacturer: ON

be limited by the EA sink current, typically 110 mA.
Optimum transient response is obtained if the compensation
components allow COMP to swing across its operating
range in 1 cycle.
Line Under and Overvoltage Detector
(UV) and overvoltage (OV) shutdown circuits. The UV and
OV thresholds are 2.5 V. A fault is present if the UV is below
2.5 V or if the OV voltage is above 2.5 V. The UV/OV
detectors incorporate 175 mV hysteresis to prevent noise
from triggering the shutdown circuits.
resistor divider from the input line as shown in Figure 34.
The UV/OV pins should be bypassed using a capacitor to
prevent triggering the UV or OV circuits during normal
switching operation.
once V
or OV fault is present, switching is not allowed and the
COMP pin is effectively grounded.
function if UV or OV functions are not needed. For example,
the UV/OV detectors can be used to implement an enable or
disable function. If positive logic is used, the enable signal
is applied to the UV pin while the OV pin is grounded. If
negative logic is used, the disable signal is applied to the OV
pin while biasing the UV pin from V
divider.
Oscillator
its frequency is set by the external timing capacitor (C
connected to the C
operation, free running and synchronized (sync). While in
free running mode, an internal current source sequentially
charges and discharges C
between 3.0 V and 3.5 V. Under normal operating
conditions, the charge (I
currents are typically 215 mA and 645 mA, respectively. The
charge:discharge current ratio of 1:3 discharges
of the total period. The Power Switch is disabled while C
The NCP103x incorporates individual line undervoltage
The UV/OV circuits can be biased using an external
The resistor divider must be sized to enable the controller
Either of these comparators can be used for a different
The oscillator is optimized for operation up to 1 MHz and
in
is within the required operating range. While a UV
Figure 34. UV/OV Resistor Divider
V
+
OV
−
from the Input Line
T
pin. The oscillator has two modes of
CT(C)
T
V
in
generating a voltage ramp
R
R
R
1
2
3
) and discharge (I
CC
V
+
UV
−
using a resistor
C
NCP1030, NCP1031
T
in 25 %
http://onsemi.com
CT(D)
T
T
)
)
14
is discharging, guaranteeing a maximum duty cycle of 75 %
as shown in Figure 35.
frequency and C
I
operating frequency by the same factor.
by capacitively coupling a synchronization pulse into the C
pin. In sync mode, the voltage on the
driven above 3.5 V to trigger the internal comparator and
complete the C
pin before it reaches 3.5 V will reduce the p−p amplitude of
the C
below the target sync frequency to maintain an adequate
voltage range and provide good noise immunity. A possible
circuit to synchronize the oscillator is shown in Figure 37.
Ramp
CT(D)
3.5 V
3.0 V
Figure 18 shows the relationship between the operating
The oscillator can be synchronized to a higher frequency
The oscillator frequency should be set no more that 25%
C
Figure 36. External Frequency Synchronization
Figure 37. External Frequency Synchronization
Power Switch
T
T
Figure 35. Maximum Duty Cycle vs COMP
C
are reduced by a factor of 7, thus reducing the
Ramp as shown in Figure 36.
C
T
Enabled
T
Free Running
Charge
Signal
Ramp
Mode
T
T1 (f1)
T
charging period. However, pulsing the C
. If an UV fault is present, both I
75%
5 V
Waveforms
R1
Sync Pulse
Circuit.
C1
COMP
25 %
C
T2 (f2)
R2
T
Sync Mode
Comparator
3.0 V/3.5 V
C
Duty Cycle
T
Reset
Range in Sync
T2 (f2)
pin needs to be
Max
C
C
T
2
T
Voltage
CT(C)
and
T
T