LM2640MTC-ADJ National Semiconductor, LM2640MTC-ADJ Datasheet - Page 13

• Manufacturer Part Number: LM2640MTC-ADJ
• Description: Dual Adjustable Step-Down Switching Power Supply Controller
• Manufacturer: National Semiconductor

Application Information
It must be understood that the maximum allowable current of
50mA must include the current drawn by the gate drive cir-
cuitry. This means that the maximum current available for
use at the LIN pin is 50 mA minus whatever is being used in-
ternally for gate drive.
The amount of current used for gate drive by each switching
output can be calculated using the formula:
Where:
I
Q is the gate charge required by the selected FET (see FET
data sheet: Gate Charge Characteristics).
F
Example: As shown in the typical application, if the FET
NDS8410 is used with the LM2640, the turn-on gate voltage
(V
sheet, the curve Gate Charge Characteristics shows that the
gate charge for this value of V
Assuming 200 kHz switching frequency, the gate drive cur-
rent used by each switching output is:
If both outputs are switching, the total gate drive current
drawn would be twice this (19.2 mA).
Note that in cases where the voltage at switching output # 1
is 4.8V or higher, the internal gate drive current is obtained
from that output (which means the full 50 mA is available for
external use at the LIN pin).
SYNC Pin
The basic operating frequency of 200 kHz can be increased
to up to 400 kHz by using the SYNC pin and an external
CMOS or TTL clock. The synchronizing pulses must have a
minimum pulse width of 200 ns.
If the sync function is not used, the SYNC pin must be con-
nected to the LIN pin or to ground to prevent false triggering.
Current Limit Circuitry
The LM2640 is protected from damage due to excessive out-
put current by an internal current limit comparator, which
monitors output current on a cycle-by-cycle basis. The cur-
rent limiter activates when ever the absolute magnitude of
the voltage developed across the output sense resistor ex-
ceeds 100 mV (positive or negative value).
If the sensed voltage exceeds 100 mV, the high-side FET
switch is turned OFF. If the sensed voltage goes below -100
mV, the low-side FET switch is turned OFF. It should be
noted that drawing sufficient output current to activate the
current limit circuits can cause the output voltage to drop,
which could result in a under-voltage latch-OFF condition
(see next section).
Under-voltage/Over-voltage Protection
The LM2640 contains protection circuitry which activates if
the output voltage is too low (UV) or too high (OV). In the
event of either a UV or OV fault, the LM2640 is latched off
and the high-side FET is turned off, while the low-side FET is
turned on.
GD
OSC
GS
is the gate drive current supplied by V
) is 5V − V
is the switching frequency.
I
GD
DIODE
= 2 X Q X F
= 2 X (24 X 10
= 9.6 mA
I
GD
= 4.3V. Referring to the NDS8410 data
= 2 X Q X F
OSC
GS
−9
is about 24 nC.
) X (2 X 10
OSC
(Continued)
LIN
.
5
)
13
If the output voltage drops below 70% of nominal value, the
under-voltage comparator will latch OFF the LM2640. To re-
store operation, power to the device must be shut off and
then restored.
It should be noted that the UV latch provides protection in
cases where excessive output current forces the output volt-
age down. The UV latch circuitry is disabled during start-up.
If the output voltage exceeds 150% of nominal, the
over-voltage comparator latches off the LM2640. As stated
before, power must be cycled OFF and then ON to restore
operation.
It must be noted that the OV latch can not protect the load
from damage in the event of a high-side FET switch failure
(where the FET shorts out and connects the input voltage to
the load).
Protection for the load in the event of such a failure can be
implemented using a fuse in the power lead. Since the
low-side FET switch turns ON whenever the OV latch acti-
vates, this would blow a series fuse if the FET and fuse are
correctly sized.
Soft-Start
An internal 5 µA current source connected to the soft-start
pins allows the user to program the turn-on time of the
LM2640. If a capacitor is connected to the SS pin, the volt-
age at that pin will ramp up linearly at turn ON. This voltage
is used to control the pulse widths of the FET switches.
The pulse widths start at a very narrow value and linearly in-
crease up to the point where the SS pin voltage is about
1.3V. At that time, the pulse-to-pulse current limiter controls
the pulse widths until the output reaches its nominal value
(and the PWM current-mode control loop takes over).
The LM2640 contains a digital counter (referenced to the os-
cillator frequency) that times the soft-start interval. The maxi-
mum allotted SS time period is 4096 counts of the oscillator
clock, which means the time period varies with oscillator fre-
quency:
If the output voltage does not move to within −1% of nominal
in the period of 4096 counts, the device will latch OFF. To re-
store operation, the power must be cycled OFF to ON.
Minimum Pulse Width
As the input voltage is increased, the pulse widths of the
switching FET’s decreases. If the pulse widths become nar-
rower than 350 ns, pulse jitter may occur as the pulses alter-
nate with slightly different pulse widths. This is does not af-
fect regulator stability or output voltage accuracy.
Loop Compensation
The LM2640 must be properly compensated to assure
stable operation and good transient response. As with any
control loop, best performance is achieved when the com-
pensation is optimized so that maximum bandwidth is ob-
tained while still maintaining sufficient phase margin for good
stability.
Best performance for the LM2640 is typically obtained when
the loop bandwidth (defined as the frequency where the loop
gain equals unity) is in the range of F
In the discussion of loop stability, it should be noted that
there is a high-frequency pole f
be approximated by:
f
Where:
p
(HF)
z
max. allowable SS interval = 4096 / F
F
OSC
/2 X Q
S
(Assumes Q
p
(HF), whose frequency can
S
OSC
<
0.5)
/10 to F
OSC
www.national.com
OSC
/5.