TZA3044T Philips Semiconductors, TZA3044T Datasheet - Page 3

• Manufacturer Part Number: TZA3044T
• Description: 1.25 Gbits/s Gigabit Ethernet postamplifiers
• Manufacturer: Philips Semiconductors

Philips Semiconductors
PINNING
1998 Jul 07
SUB
TEST
AGND
DIN
DINQ
V
CF
JAM
STQ
ST
DGND
DOUTQ
DOUT
V
V
RSET
SYMBOL
CCA
CCD
ref
1.25 Gbits/s Gigabit Ethernet postamplifiers
PIN
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
substrate
test pin
ground
analog input
analog input
supply
analog input
PECL input
PECL output
PECL output
ground
PECL output
PECL output
supply
analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 k
analog input
TYPE
substrate pin; must be at the same potential as AGND (pin 3)
for test purpose only; to be left open in the application
analog ground; must be at the same potential as DGND (pin 11)
differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DINQ (pin 5)
differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DIN (pin 4)
analog supply voltage; must be at the same potential as V
filter capacitor for input signal level detector; capacitor should be connected
between this pin and V
PECL-compatible input; controls the output buffers DOUT and DOUTQ
(pins 13 and 12). When a LOW signal is applied, the outputs will follow the input
signal. When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into
LOW and HIGH states, respectively. When left unconnected, this pin is actively
pulled LOW (JAM OFF).
PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is HIGH;
complimentary to ST (pin 10)
PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is LOW;
complimentary to STQ (pin 9)
digital ground; must be at the same potential as AGND (pin 3)
PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a HIGH condition; complimentary to DOUT (pin 13)
PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a LOW condition; complimentary to DOUTQ (pin 12)
digital supply voltage; must be at the same potential as V
input signal level detector programming; nominal DC voltage is V
threshold level is set by connecting an external resistor between RSET and V
or by forcing a current into RSET; default value for this resistor is 180 k which
corresponds with approximately 4 mV (p-p) differential input signal
3
CCA
(pin 6)
DESCRIPTION
TZA3044T; TZA3044U
CCA
CCD
Objective specification
(pin 6)
(pin 14)
CCA
1.5 V;
CCA