ML4818CS Micro Linear, ML4818CS Datasheet - Page 8

• Manufacturer Part Number: ML4818CS
• Description: Phase Modulation/Soft Switching Controller
• Manufacturer: Micro Linear

ML4818
CURRENT LIMIT, FAULT DETECTION AND SOFT START
Current limit is implemented when the current sensed on
I
terminated. The flip flop (Figure 10) turns on the current
source to charge C
the clock period. When C
start reset occurs. The number of times the PWM cycle is
terminated due to over-current is “remembered” on C
Over time, C
measure of “forgetting” when the over-current condition
no longer occurs. This integrating fault detection is useful
in differentiation between short circuit and load surge
conditions.
8
LIM
V(PIN 12)
V(PIN 4)
reaches the 1V limit. At this point, the PWM cycle is
3.4V
1V
Figure 11a, 11b. I
Waveforms During Short Circuit.
RST
is discharged by R
RST
and remains on for the duration of
Figure 10. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
I
LIMIT
R
SWITCH
R
RST
RST
SENSE
has charged to 3.4V, a soft
R1
and Resulting RC
C
RST
SS
C
RST
providing a
C1
12
9
4
RESET
SOFT START
I
LIM
I2
RC
V+
RESET
RST
.
1V
Since the per cycle charge on RC
how early in the power cycle the over-current occurs, a
reset will occur more quickly under output short circuit
conditions (Figures 11a and 11b) than during a load surge
(Figures 11c and 11d).
When the soft start reset occurs, the output is inhibited
and the soft start capacitor is discharged. The output will
remain off until C
providing a reset delay. When the IC restarts, the error
amplifier output voltage is limited to the voltage at SOFT
START, thus limiting the duty cycle.
V(PIN 12)
V(PIN 4)
3.4V
1.3V
+
–
3.4V
1V
Figure 11c, 11d. I
+
–
Waveforms During Load Surge.
Q
PWM CYCLE
TERMINATE
RST
R
S
I
1
discharges to 1.3V through R
V+
LIMIT
CLOCK
UNDER-VOLTAGE
LOCKOUT
and Resulting RC
RESET
OUTPUT
INHIBIT
is proportional to
RESET
RST
,