P80C557E4 Philips Semiconductors, P80C557E4 Datasheet
P80C557E4
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P80C557E4 Summary of contents
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... P83C557E4/P80C557E4/P89C557E4 Single-chip 8-bit microcontroller Product specification Supersedes data of 1999 Feb 15 INTEGRATED CIRCUITS 1999 Mar 02 ...
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... The P8xC557E4 has the same instruction set as the 80C51. Three versions of the derivative exist: P83C557E4 — 32 Kbytes mask programmable ROM P80C557E4 — ROMless version of the P83C557E4 P89C557E4 — 32 Kbytes FEEPROM (Flash-EEPROM) The P8xC557E4 contains a non-volatile 32 Kbytes mask ...
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... TIMER/ PORTS CAPTURE EVENT LATCHES COUNT- ERS CT0I-CT3I T2 RT2 6 NOT PRESENT IN P80C557E4 7 ONLY PRESENT IN P89C557E4 Figure 1. Block diagram P8xC557E4 3 Product specification FREQUENCY RANGE TEMPERATURE (MHz) RANGE ( C) 3 +70 3 –40 to +85 3 +70 3 –40 to +85 3 ...
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... XTAL1 XTAL2 EA ALE/WE PSEN AVref+ AVref– ADEXS PWM0 PWM1 SCL SDA ADC0-7 CMSR0-5 CMT0 CMT1 RSTIN RSTOUT EW *) only P89C557E4 with alternate function WE 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 XTAL3 XTAL4 SELXTAL1 ...
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... PWM0 17 PWM1 18 EW P4.0/CMSR0 19 20 P4.1/CMSR1 21 P4.2/CMSR2 22 P4.3/CMSR3 RSTOUT 23 24 P4.4/CSMR4 n.c. = not connected * = only P89C557E4 with alternate function WE Figure 3. Pinning diagram for QFP80 (SOT318) 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 P8xC557E4 ...
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... SDA 40 I C-bus serial data I/O port If SCL and SDA are not used, they must be connected to V 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Alternative function Eight input channels to ADC (ADC0–ADC7) Alternative function CMSR0 } CMSR1 } CMSR2 } compare and set/reset CMSR3 } outputs on a match with timer T2 ...
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... PLL is selected for clocking of the controller, using the XTAL3/ XTAL4 crystal. NOTE avoid a ‘latch-up’ effect at Power-on, the voltage at any pin at any time must not be higher or lower than V respectively. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Alternative function RXD : Serial input port TXD ...
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... Internal External ( ( Program Memory 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 6. FUNCTIONAL DESCRIPTION 6.1 General The P8xC557E4 is a stand-alone high-performance microcontroller designed for use in real time applications such as instrumentation, industrial control, medium to high-end consumer applications and specific automotive control applications. ) with SS In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these applications ...
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... RAM 128 to 255 SFR 128 to 255 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 – RAM 128 to 255 can only be addressed indirectly. Address pointers are R0 and R1 of the selected registerbank. – AUX-RAM 0 to 767 is also indirectly addressable as external DATA MEMORY locations 0 to 767 via MOVX-Datapointer instruction, unless it is disabled by setting ARD = 1. ...
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... NOTE: 1. ARD (AUX-RAM Disable bit in the Special Function Register PCON 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 255 767 (XRAMP 512 0 511 255 (XRAMP 256 255 255 (XRAMP Figure 6 ...
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... The first three methods can be used for addressing destination operands. Most instructions have a “destination/source” field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 HIGH NIBBLE OF SFR ADDRESS ...
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... Mar 02 P83C557E4/P80C557E4/P89C557E4 BIT ADDRESS (HEX ...
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... A0H A7 A6 SM0 SM1 98H 9F 9E 90H 97 96 TF1 TR1 88H 80H Figure 8. Special Function Register bit addresses 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 BIT ADDRESS (HEX) PCM1 PCM0 PCT3 PCT2 PCT1 ECM1 ECM0 ECT3 ECT2 ECT1 ...
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... P1 is turned on for 2 system clock periods after QN makes a 1-to-0 transition. During this time, P1 also turns on P3 through the inverter to form an additional pull up. Figure 9. I/O buffers in the P8xC557E4 (Ports and 4) 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Port 4 : can be configured to provide signals indicating a match between timer counter T2 and its compare registers. ...
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... BIT LOW/HIGH ration of PWM0 signal = PWM0 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 conventional operational amplifier circuitry. If the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the PWM outputs before they are integrated. The repetition frequency fpwm, at the PWMn outputs is ...
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... PWM1 (FDH) PWM1.7 PWM1.6 Table 8. Description of PWM1 bits BIT LOW/HIGH ration of PWM1 signal = PWM1 CLK 1/2 Figure 13. Functional Diagram of Pulse Width Modulated Outputs. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 PWM1.5 PWM1.4 PWM1.3 Figure 12. Pulse width register PWM1. FUNCTION (PWM1) 255 – (PWM1) ...
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... ADCON (D7H) ADPR1 ADPR0 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Start of a conversion by software or with an external signal. Eight 10-bit buffer registers, one register for each analog input channel. Interrupt request after one channel scan loop. Programmable prescaler (dividing adapt to (typical +5V) ...
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... A rising edge at input ADEXS has no effect. ADCON.0 ADSFE falling edge at input ADEXS will start the A/D conversion and generate a capture signal falling edge at input ADEXS has no effect. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 COMPARATOR ANALOG Mux. + – DAC 10–bit result ADCON Read ADRSH ...
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... ADRSLn first and after it the register ADRSH. 7 ADRSLn ADRSn.7 ADRSn.6 (n: 0...7) 7 ADRSH 0 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 ADPSS5 ADPSS4 ADPSS3 0 = The corresponding analog input is skipped in the auto-scan loop The corresponding analog input is included in the auto-scan loop. ...
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... ADPR0 in register ADCON to adapt the conversion time for different microcontroller clock frequencies. Table 11 shows conversion times (tconv) for one A/D conversion at some convenient system clock frequencies (fclk) and ADC prescaler divisors (m), which are user selectable by the bits ADCON.7/ADPR1 and ADCON.6/ADPR0. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 P5.6 P5.5 P5 ...
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... For input voltages between AV (AV + 1/2 LSB) the 10-bit conversion result code will be ref– 00 0000 0000 B = 000H = 0D. For input voltages between 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 (AV – 3/2 LSB) and AV ref 1111 1111 B = 3FFH = 1023D. The result code corresponding to an analog input voltage (AV ...
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... Timer/Counter 1 stopped. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Both internal and external inputs can be gated to the counter by a second external source for directly measuring pulse durations. When configured as a counter, the register is incremented on every falling edge on the corresponding input pin T1. The ...
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... Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. IE0 TCON.1 Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 TR1 TF0 TR0 IE1 ...
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... T P4.7 STE RTE 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 byte while T2 is being read not loadable and is reset by the RST signal or at the positive edge of the input signal RT2, if enabled. In the Idle or Power-down Mode the timer/counter and prescaler are reset and halted connected to four 16-bit Capture Registers: CT0, CT1, CT2 and CT3 ...
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... Table 17. Timer 2 mode select T2MS1 T2MS0 0 0 Timer T2 halted (off clock source = Test mode; do not use clock source = pin T2 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 T2IS0 T2ER T2BO T2P1 Figure 22. T2 control register (TM2CON). FUNCTION TIMER T2 CLOCK MODE SELECTED /12 CLK 25 ...
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... TM2IR.4 CM0 interrupt flag CTI3 TM2IR.3 CT3 interrupt flag CTI2 TM2IR.2 CT2 interrupt flag CTI1 TM2IR.1 CT1 interrupt flag CTI0 TM2IR.0 CT0 interrupt flag 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 CTP3 CTN2 CTP2 CTN1 Figure 23. Capture control register (CTCON). FUNCTION CMI2 ...
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... For more information concerning the TM2CON, CTCON, TM2IR and the STE/RTE registers see IC20 handbook, chapter “80C51 family hardware description”. Port 4 can be read and written by software without affecting the toggle, set and reset signals byte overflow of the least 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 TG46 ...
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... Clear Write T3 EW 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 produce a reset upon overflow thus preventing the processor running out of control. The watchdog timer can only be reloaded if the condition flag WLE = PCON.4 has been previously set by software. At the moment the counter is loaded the condition flag is automatically cleared. The time interval between the timer’ ...
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... The receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Mode 2: 11 bits are transmitted through TXD or received through RXD: a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1) ...
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... Fault diagnostics and debugging are simple; malfunctions can be immediately traced 2 For more information on the I C-bus specification (including fast-mode) please refer to the Philips publication number 9398 393 40011 and/or the 80C51 Data Handbook IC20. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 MODE DESCRIPTION 0 Shift register 1 8-bit UART 2 ...
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... Philips Semiconductors Single-chip 8-bit microcontroller SDA ARBITRATION + SYNC LOGIC SCL Figure 29. Block diagram of I 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 7 1 SLAVE ADDRESS S1ADR 7 SHIFT REGISTER S1DAT BUS CLOCK GENERATOR 7 S1CON 7 S1STA 2 C serial I/O interface. 31 Product specification ...
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... A data byte is received. while the device is a selected slave receiver. When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received. CR1 S1CON.1 Clock rate bits 1 and 0, see Table 25. CR0 S1CON.0 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 ENS1 STA STO SI Figure 30 ...
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... SLA and W have been transmitted, ACK received 28H DATA and S1DAT has been transmitted, ACK received 30H DATA and S1DAT has been transmitted, ACK received 38H Arbitration lost in SLA, R/W or DATA 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 BIT RATE (kHz 12MHz 3. ...
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... R : Read bit W : Write bit ACK : Acknowledgement (acknowledge bit = 0) ACK : Not acknowledgement (acknowledge bit = 1) 2 DATA : 8-bit data byte to or from I C-bus MST : Master SLV : Slave TRX : Transmitter REC : Receiver 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 34 Product specification ...
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... S1ADR (DBH) SLA6 Table 32. Description of S1ADR bits SYMBOL BIT SLA6 to 0 S1ADR Own slave address GC S1ADR general call address is not recognized 1 = general call address is recognized 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 S1DAT.5 S1DAT.4 S1DAT.3 Figure 32. Data shift register SLA5 ...
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... If a capture register is unused and it’s contents interest, then the corresponding input pin CTnI/P1.n (n: 0...3) may be used as a (configurable) positive and/or negative edge triggered additional external interrupt input (INT2, INT3, INT4, INT5). 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 The ADC Interrupt is generated by bit ADINT, which is set when of all selected analog inputs to be scanned, the conversion is finished. ...
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... EX0 IEN0.0 Enable External interrupt 0 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 interrupt flags. An external interrupt flag (IE0 or IE1) is cleared only if it was transition-activated. All other interrupt flags are not cleared by hardware and must be cleared by the software. The LCALL pushes the contents of the program counter on to the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 38 ...
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... Capture 1 Timer 2 Compare 1 Timer 1 Overflow CT2I Timer 2 Capture 2 Timer 2 Compare 2 T UART Serial Port R CT3I Timer 2 Capture 3 Timer T2 Overflow 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Interrupt priority Global enable registers Figure 35. The interrupt system. 38 Product specification Polling hardware ...
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... PT1 IP0.3 Timer 1 interrupt priority level PX1 IP0.2 External interrupt 1/Seconds interrupt priority level PT0 IP0.1 Timer 0 interrupt priority level PX0 IP0.0 External interrupt 0 priority level 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 ECM2 ECM1 ECM0 ECT3 Figure 36. Interrupt enable register (IEN1). FUNCTION 6 5 ...
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... Timer 1 overflow SIO0 (UART) 2 SIO1 (I C) Timer 2 capture 0 Timer 2 capture 1 Timer 2 capture 2 Timer 2 capture 3 ADC completion Timer 2 compare 0 Timer 2 compare 1 Timer 2 compare 2 Timer 2 overflow 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 PCM2 PCM1 PCM0 PCT3 Figure 38. Interrupt priority register (IP1). FUNCTION NAME X0 S1 ADC ...
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... Power-down External 0 0 NOTE Idle Mode SCL and SDA can be active as outputs only if SIO1 is enabled; if SIO1 is disabled (S1CON.6/ENS1 = 0) these pins are in a high-impedance state. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 ARD RFI WLE GF1 Figure 39. Power control register (PCON). ...
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... The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to PCON.0. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 SELXTAL1 XTAL3 PLL Osc ...
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... 20pF Figure 42. Using the On-Chip Oscillator. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 gives the possibility to exit Power-down without changing the port output levels. To terminate the Power-down Mode with an external interrupt, INT0 or INT1 must be switched to be level-sensitive and must be enabled. The external interrupt input signal INT0 or INT1 must be kept LOW till the oscillator has restarted and stabilized (see Figure 41) ...
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... Baud, when using the UART and Timer1. NOTE: 1. This parameter is characterized. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 The system clock frequency f of the PLLCON bits FSEL(4:0) (see Table 41). If only FSEL(4:2) is changed but not FSEL(1:0), then it takes about 1us until the new frequency is available. ...
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... Reset or after Wake-up from XTAL4 C RUN32 PD RSTIN 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Power-down. It controls the stretching of the reset pulse to the microcontroller and controls releasing the system clock to the microcontroller. A RSTIN signal of 1us at minimum will reset the microcontroller. In case of Reset or Wake-up with halted 32kHz oscillator: From ...
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... On-chip R RST resistor SELXTAL1 Figure 46. On-chip Reset Configuration 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 6.15 Power-on Reset An automatic Reset can be obtained by switching on V RSTIN pin is connected to V Figure 47. Is the HF oscillator selected the V ms and the capacitor should be at least 2.2 F. The decrease of the RSTIN pin voltage depends on the capacitor and the internal resistor R ...
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... Program Memory (in-code 8 bit or 16 bit constant) Base-Register-plus Index-Register-Indirect Addressing – Program Memory look-up table (@DPTR+A, @PC+A) The first three addressing modes are usable for destination operands. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 7.1.1 80C51 Family Instruction Set Table 42. Instruction that affect Flag settings INSTRUCTION FLAG C ...
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... OR immediate data to Accumulator ORL direct,A OR Accumulator to direct byte ORL direct,#data OR immediate data to direct byte XRL A,Rn Exclusive-OR register to Accumulator XRL A,direct Exclusive-OR direct byte to Accumulator XRL A,@Ri Exclusive-OR indirect RAM to Accumulator 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 DESCRIPTION BYTE / CYCLES ...
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... Pop direct byte from stack XCH A,Rn Exchange register with Accumulator XCH A,direct Exchange direct byte with Accumulator XCH A,@Ri Exchange indirect RAM with Accumulator XCHD A,@Ri Exchange low-order digit indirect RAM with ACC 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 DESCRIPTION BYTE / CYCLES ...
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... Compare immediate to indirect and jump if not equal DJNZ Rn,rel Decrement register and jump if not zero DJNZ direct,rel Decrement direct byte and jump if not zero NOP No operation NOTE: All mnemonics copyrighted Intel Corporation 1980 1. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 DESCRIPTION BYTE / CYCLES ...
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... SETB dir addr11 bit E MOVX AJMP MOVX A, @Ri A, @DPTR addr11 0 F MOVX ACALL MOVX A, @Ri, A @DPTR, A addr11 0 *) MOV A, ACC is not a valid instruction 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 second hexadecimal character of opcode INC INC INC @ dir 0 RRC DEC DEC DEC @ ...
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... Two bits UBS1 and UBS0 of the FEEPROM control special function register FMCON select between the two memory blocks. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 User program memory selection If UBS1 and UBS0 are both 0, then the user program memory is mapped into the 64 K program memory space and the boot ROM cannot be selected ...
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... In the program execution between 63k and 64k setting of UBS bits is not allowed. USER MODE RST PSEN ALE/WE EA UBS1, UBS0 0,0 Start at 0000H in user program Figure 48. Program memory map and operation modes 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 0,0 External Program Memory ( UBS1, UBS0 User-Boot selection bits in FMCON BOOT MODE internal external ...
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... V = verified byte (read back LSB’s of DPTR are don’t care LSB’s of DPTR are “0” LSB’s of DPTR are don’t care LSB’s of DPTR contain 08H. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 UBS0 HV – ...
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... CONTENT 30H 15H 31H B5H 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 8.4 Security The security feature protects against software piracy and prevents that the content of the FEEPROM can be read undesirable. The Security Byte is located in the highest address location 7FFFH of the FEEPROM. The Security Byte should be 50H to activate and 00H or FFH to deactivate the security feature ...
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... Philips Semiconductors Single-chip 8-bit microcontroller 1 DON’T CARE 4-6MHz 1 A0– 4-6MHz 1 A0- 4-6MHz 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 +5 V SELXTAL1 RSTIN EA P3.6 ALE/WE P3.7 PSEN P89C557E4 XTAL2 P2.7 P2.6 XTAL1 P2.0-P2.5 V P3.4 SS Figure 50. Erase Configuration +5 V SELXTAL1 RSTIN EA P3.6 ALE/WE P3.7 PSEN ...
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... AVWL ALE/WE t EHWL P2.7 ENABLE * For ERASE conditions see Figure 50. For PROGRAM conditions see Figure 51. For VERIFY conditions see Figure 52. Figure 53. FEEPROM Programming/Erase and Verification Waveforms 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 = 0 V (see Figure 53) SS MIN 4 48t CLK 48t CLK 48t CLK 48t CLK ...
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... FEEPROM by a reset for user mode (EA = high, PSEN not affected). If the programming was not successful the boot program halts and a retry can be started by a reset for the boot mode. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 + P89C557E4 P3 ...
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... This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions are taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 PARAMETER 59 Product specification RATING UNIT – ...
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... OH V Output high voltage (Port 0 in external bus mode, ALE, OH1 PSEN, PWM0, PWM1, RSTOUT) V Hysteresis of Schmitt Trigger inputs SCL, SDA (Fast-mode) HYS NOTES: See Page 62. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 TEST CONDITIONS See notes 1 and 16MHz CLK See notes 1 and 3 ...
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... G Gain error Absolute voltage error e M Channel to channel matching CTC C Crosstalk between inputs of port 5 t NOTES: See Page 62. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 TEST CONDITIONS Test freq = 1MHz amb See note 6 TEST CONDITIONS Port ...
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... EA = RSTIN = ADEXS = SELXTAL 1 = XTAL1 = V DD 18. Not 100% tested; sum of A (PLL) and A IID 2 19. The parameter meets the I C bus specification for standard-mode and fast-mode devices. 20. Not 100% tested. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 test conditions – 0.5 V; XTAL2, XTAL3 not connected ADEXS = XTAL4 = – ...
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... Philips Semiconductors Single-chip 8-bit microcontroller (mA (1) Maximum operating mode P89C557E4 (2) Maximum operating mode P83C557E4/P80C557E4 (3) Maximum Idle Mode P89C557E4 (4) Maximum Idle Mode P83C557E4/P80C557E4 Figure 55. Supply Current (I 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 (MHz Function of Frequency at XTAL1 DD 63 Product specification ...
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... Offset error OS e (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DL e (4) Integral non-linearity ( (5) Center of a step of the actual transfer curve. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 (2) (1) (5) (4) (3) 1 LSB (ideal 1018 1019 1020 1 LSB = ). Figure 56. ADC Conversion Characteristic ...
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... Output data hold after clock rising edge XHQX t 64 Input data hold after clock rising edge XHDX t 64 Clock rising edge to input data valid XHDV 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 12MHz CLOCK 16MHz CLOCK MIN MAX MIN MAX 127 234 ...
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... CLK t XTAL1 HIGH time CLKH t XTAL1 LOW time CLKL t XTAL1 rise time CLKR t XTAL1 fall time CLKF 1) t Controller cycle time CYC NOTE CYC CLK 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 Standard-mode 2 I C-bus MIN MAX MIN 0 100 4.7 – 1.3 4.0 – 0.6 4.7 – 1.3 4.0 – 0.6 4.7 – ...
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... Timing measurements are made at 2.0 V for a logic ‘HIGH’ and 0.8 V for a logic ‘LOW’. Figure 58. AC Testing Input/Output t LHLL ALE t AVLL PSEN A0–A7 PORT 0 PORT 2 Figure 60. External Program Memory Read Cycle 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 t t CLKH CLKR V V IH1 IH1 0.8V 0.8V t CLKL t CLK Figure 57 ...
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... FROM RI OR DPL t AVWL PORT 2 ALE PSEN t LLWL LLAX AVLL A0–A7 PORT 0 FROM RI OR DPL t AVWL PORT 2 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 t WHLH t LLDV t RLRH t RHDZ t RLDV t RHDX t RLAZ DATA IN t AVDV P2.0–P2.7 OR A8–A15 FROM DPH Figure 61. External Data Memory Read Cycle ...
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... ALE t XLXL CLOCK t t QVXH OUTPUT DATA 0 WRITE TO SBUF t XHDV INPUT DATA VALID CLEAR RI Figure 64. UART waveforms in Shift Register Mode 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 repeated START condition STOP condition SU;DAT1 HD;DAT 2 Figure 63. Timing SIO1 (I C) Interface XHQX 1 2 ...
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... PORT INPUT SERIAL PORT CLOCK Purchase of Philips I to use the components in the specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 One Machine Cycle One Machine Cycle ...
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... Philips Semiconductors Single-chip 8-bit microcontroller QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 2.7 mm; high stand-off height 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 71 Product specification SOT318-1 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1999 Mar 02 P83C557E4/P80C557E4/P89C557E4 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 72 Product specification All rights reserved. Printed in U.S.A. Date of release: 03-99 ...