COP8CBR9 National Semiconductor, COP8CBR9 Datasheet - Page 63

• Manufacturer Part Number: COP8CBR9
• Description: 8-Bit CMOS Flash Microcontroller with 32k Memory/ Virtual EEPROM/ 10-Bit A/D and Brownout
• Manufacturer: National Semiconductor

17.0 WATCHDOG/Clock Monitor
17.3 WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
• Both the WATCHDOG and CLOCK MONITOR detector
• Following RESET, the WATCHDOG and CLOCK MONI-
• The WATCHDOG service window and CLOCK MONI-
• The initial WATCHDOG service must match the key data
• Subsequent WATCHDOG services must match all three
• The correct key data value cannot be read from the
• The WATCHDOG detector circuit is inhibited during both
• The CLOCK MONITOR detector circuit is active during
• The WATCHDOG service window will be set to its se-
• The IDLE timer T0 is not initialized with external RESET.
• The user can sync in to the IDLE counter cycle with an
• A hardware WATCHDOG service occurs just as the de-
• Following RESET, the initial WATCHDOG service (where
• When using any of the ISP functions in Boot ROM, the
(Continued)
circuits are inhibited during RESET.
TOR are both enabled, with the WATCHDOG having the
maximum service window selected.
TOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
value in the WATCHDOG Service register WDSVR in
order to avoid a WATCHDOG error.
data fields in WDSVR in order to avoid WATCHDOG
errors.
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
the HALT and IDLE modes.
both the HALT and IDLE modes. Consequently, the de-
vice inadvertently entering the HALT mode will be de-
tected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program). Likewise, a device with WATCHDOG en-
abled in the Option but with the WATCHDOG output not
connected to RESET, will draw excessive HALT current if
placed in the HALT mode. The clock Monitor will pull the
WATCHDOG output low and sink current through the
on-chip pull-up resistor.
lected value from WDSVR following HALT. Consequently,
the WATCHDOG should not be serviced for at least 2048
Idle Timer clocks following HALT, but must be serviced
within the selected window to avoid a WATCHDOG error.
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the selected bit of
the IDLE counter toggles (every 4, 8, 16, 32 or 64k Idle
Timer clocks). The user is responsible for resetting the
T0PND flag.
vice
WATCHDOG should not be serviced for at least 2048 Idle
Timer clocks following IDLE, but must be serviced within
the selected window to avoid a WATCHDOG error.
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed any-
where within the maximum service window (65,536 in-
struction cycles) initialized by RESET. Note that this initial
WATCHDOG service may be programmed within the ini-
tial
WATCHDOG error.
ISP routines will service the WATCHDOG within the se-
2048
exits
instruction
the
IDLE
cycles
mode.
without
Consequently,
causing
the
a
63
17.4 DETECTION OF ILLEGAL CONDITIONS
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of unprogrammed ROM gets zeros. The opcode for
software interrupt is 00. If the program fetches instructions
from unprogrammed ROM, this will force a software inter-
rupt, thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each
return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more re-
turns than calls, the stack pointer will point to addresses 070
and 071 Hex (which are undefined RAM). Undefined RAM
from addresses 070 to 07F (Segment 0), and all other seg-
ments (i.e., Segments 4... etc.) is read as all 1’s, which in
turn will cause the program to return to address 7FFF Hex.
The Option Register is located at this location and, when
accessed by an instruction fetch, will respond with an INTR
instruction (all 0’s) to generate a software interrupt, signalling
an illegal condition on overpop of the stack.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined Program Memory
2. Over “POP”ing the stack by having more returns than
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restart-
ing (this recovery program is probably similar to that follow-
ing reset, but might not contain the same program initializa-
tion procedures). The recovery program should reset the
software interrupt pending bit using the RPND instruction.
18.0 MICROWIRE/PLUS
MICROWIRE/PLUS is a serial SPI compatible synchronous
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with MICROWIRE/PLUS
or SPI peripherals (i.e. A/D converters, display drivers,
EEPROMs etc.) and with other microcontrollers which sup-
port the MICROWIRE/PLUS or SPI interface. It consists of
an 8-bit serial shift register (SIO) with serial data input (SI),
serial data output (SO) and serial shift clock (SK). Figure 32
shows a block diagram of the MICROWIRE/PLUS logic.
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift clock
is called the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table 30 details the
different clock rates that may be selected.
lected upper window. Upon return to flash memory, the
WATCHDOG is serviced, the lower window is enabled,
and the user can service the WATCHDOG anytime fol-
lowing exit from Boot ROM, but must service it within the
selected upper window to avoid a WATCHDOG error.
calls.
www.national.com