EP7309-CR-C Cirrus Logic, EP7309-CR-C Datasheet
EP7309-CR-C
Related parts for EP7309-CR-C
EP7309-CR-C Summary of contents
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... FAX: (512) 445 7581 http://www.cirrus.com Low-Power System on Chip OVERVIEW The Maverick™ EP7309 is designed for ultra-low-power applications such as digital music players, internet appliances, smart cellular phones or any hand-held device that features the added capability of digital audio decompression. The core-logic functionality of the device is built around an ARM720T processor with four- way set-associative unified cache and a write buffer ...
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... I Package — 208-Pin LQFP — 256-Ball PBGA — 204-Ball TFBGA I The fully static EP7309 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process The EP7309 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal‚ ...
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... RISC Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7309 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7309 is powering, and then deliver the copyrighted information over a secure connection ...
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... I Photo diode input Table C. Universal Asynchronous Receiver/Transmitters Pin Assignments Digital Audio Interface (DAI) The EP7309 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly ‚ interface with the Crystal CS43L41/42/43 low-power ‚ ...
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... EINT[3] nEXTFIQ nMEDCHG/nBROM Note: Real-Time Clock The EP7309 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt. Copyright 2001 Cirrus Logic (All Rights Reserved) ...
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... EP7309 High-Performance, Low-Power System on Chip • Driven byan external 32.768 kHz crystal oscillator Pin Mnemonic Pin Description RTCIN Real-Time Clock Oscillator Input RTCOUT Real-Time Clock Oscillator Output VDDRTC Real-Time Clock Oscillator Power VSSRTC Real-Time Clock Oscillator Ground Table K. Real-Time Clock Pin Assignments PLL and Clocking • ...
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... Internal Boot ROM The internal 128 byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH. Packaging The EP7309 is available in a 208-pin LQFP package, 256- ball PBGA package or a 204-ball TFBGA package. Pin Multiplexing The following table shows the pin multiplexing of the DAI, SSI2 and the CODEC ...
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... SSIRXFR LEDDRV PHDIN CS[n] RXD1/2 WORD TXD1/2 ADCCLK nCS[2] nADCCS nCS[3] ADCOUT ADCIN LEDFLSH SMPCLK Figure 1. A Maximum EP7309 Based System Copyright 2001 Cirrus Logic (All Rights Reserved) CL1 LCD CL2 FRM M KEYBOARD POWER SUPPLY UNIT AND COMPARATORS BATTERY RUN DC-TO-DC ...
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... Copyright 2001 Cirrus Logic (All Rights Reserved) High-Performance, Low-Power System on Chip Unit Conditions + 0 2 DDIO DDIO DDIO 2 0.4 V VIL to VIH V IOH = 0 IOH = IOH = 12 mA 0.3 V IOL = –0.1 mA 0.5 V IOL = –4 mA 0.5 V IOL = –12 mA VIN = V or GND 1.0 µA DD VOUT = V or GND 100 µ EP7309 9 ...
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... All power dissipation values can be derived from taking the particular IDD current and multiplying by 2 The RTC of the EP7309 should be brought up at room temperature. This is required because the RTC OSC will NOT function properly brought up at –40 ° C. Once operational, it will continue to operate down to –20 ° C extended and 0 ° C commercial ...
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... MHz mode because the EXPCLK is provided as an input rather than generated internally. These timings are estimated at present. The timing values are referenced to 1/2 V DS507PP1 = 0 V over an operating temperature of 0 ° +70 ° C. Those characteristics SS Copyright 2001 Cirrus Logic (All Rights Reserved) High-Performance, Low-Power System on Chip EP7309 . DD 11 ...
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... EP7309 High-Performance, Low-Power System on Chip Static Memory Figure 2 through Figure 5 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes. Parameter EXPCLK rising edge to nCS assert delay time ...
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... EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. DS507PP1 t MOEd EXs EXh Copyright 2001 Cirrus Logic (All Rights Reserved) High-Performance, Low-Power System on Chip t CSh t MOEh t Dh EP7309 13 ...
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... EP7309 High-Performance, Low-Power System on Chip Static Memory Single Write Cycle EXPCLK nCS A nMWE nMOE t HWd HALF WORD t WDd WORD D EXPRDY WRITE Figure 3. Static Memory Single Write Cycle Timing Measurement Note: 1. The cycle time can be extended by integer multiples of the clock period ( MHz 18.432 MHz, and MHz), by either driving EXPRDY low and/or by programming a number of wait states ...
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... This improves performance so the SQAEN bit should always be set where possible. DS507PP1 EXs EXh Copyright 2001 Cirrus Logic (All Rights Reserved) High-Performance, Low-Power System on Chip t CSh MOEh EP7309 15 ...
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... EP7309 High-Performance, Low-Power System on Chip Static Memory Burst Write Cycle EXPCLK t CSd nCS MWd nMWE nMOE t HWd HALF WORD t WORD WDd EXs EXPRDY WRITE Figure 5. Static Memory Burst Write Cycle Timing Measurement Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive cycles that can be driven ...
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... Figure 6. SSI1 Interface Timing Measurement Copyright 2001 Cirrus Logic (All Rights Reserved) High-Performance, Low-Power System on Chip Symbol Min Max t TBD TBD Cd t TBD TBD INs t TBD TBD INh t TBD TBD Ovd t TBD TBD Od t Ovd EP7309 Unit ...
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... EP7309 High-Performance, Low-Power System on Chip SSI2 Interface Parameter SSICLK period (slave mode) SSICLK high time SSICLK low time SSICLK rise/fall time SSICLK rising edge to RX and/or TX frame sync high time SSICLK rising edge to RX and/or TX frame sync low time SSIRXFR and/or SSITXFR period ...
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... High-Performance, Low-Power System on Chip Symbol Min Max t 200 6,950 clk t 80 3,475 clk_low t 80 3,475 clk_high CL1d t 80 3,475 CL2d t 80 3,475 CL2h t 300 10,425 FRMd − − DDd t t clk_low clk_high EP7309 Unit ...
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... EP7309 High-Performance, Low-Power System on Chip JTAG Parameter TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance ...
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... EP7309 208-Pin LQFP Pin 1 Indicator 0.45 (0.018) 0.75 (0.030) Figure 10. 208-Pin LQFP Package Outline Drawing Figure 11. For pin descriptions see the EP7309 User’s Manual. Copyright 2001 Cirrus Logic (All Rights Reserved) High-Performance, Low-Power System on Chip 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1 ...
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... Figure 11. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram Note: 1. N/C should not be grounded but left as no connects. 2. Pin differences between the EP7212 and the EP7309 are bolded. 22 EP7309 208-Pin LQFP (Top View) Copyright 2001 Cirrus Logic (All Rights Reserved) ...
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... I/O 1 SSICLK I/O 1 VSSIO Pad Gnd SSITXFR I/O 1 SSITXDA O 1 SSIRXDA I SSIRXFR I/O ADCIN I nADCCS O 1 VSSCORE Core Gnd VDDCORE Core Pwr VSSIO Pad Gnd EP7309 Reset State Input Input Input Low Low Low Low Low Low Low Low Input Low Low Input High 23 ...
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... EP7309 High-Performance, Low-Power System on Chip Table S. 208-Pin LQFP Numeric Pin Listing (Continued) Pin Signal Type No. 74 VDDIO Pad Pwr 75 DRIVE[1] I/O 76 DRIVE[0] I/O 77 ADCCLK O 78 ADCOUT O 79 SMPCLK O 80 FB[ VSSIO Pad Gnd 82 FB[ COL[ COL[ COL[ COL[ COL[3] ...
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... Pad Gnd N/C I/O 2 N/C I/O 2 nMWE O 1 nMOE O 1 VSSIO Pad Gnd nCS[ nCS[ nCS[ nCS[ nCS[ EP7309 Reset State Low Low Low Low Low High High Low Low Low Low High High High High High High High 25 ...
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... EP7309 High-Performance, Low-Power System on Chip 204-Ball TFBGA Package Characteristics 204-Ball TFBGA Package Specifications TOP VIEW A1 CORNER SEATING PLANE Figure 12. 204-Ball TFBGA Package ...
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... D14 VDDR A15 D17 D18 A19 D21 HALF WORD BUZ D29 A26 VDDR COL5 COL2 COL0 D30 A27 D26 COL6 COL3 COL1 D31 D28 D27 EP7309 19 20 GNDR GNDR A GNDR nURESET B BATOK nPOR D10 F A9 D11 G D12 A12 H ...
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... EP7309 High-Performance, Low-Power System on Chip TFBGA Ball List Table T. 204-Ball TFBGA Ball List Die Pad Bond Pad Package Ball U2 U2.2 2 Y20 U2.3 3 B18 U2. U2. U2.12 12 B18 U2. U2. U2. U2. U2. U2. U2. U2. U2.21 21 Y20 U2. ...
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... F20 144 G19 145 E20 146 F19 147 G18 148 D20 149 Y3 150 F18 151 D19 152 E19 153 C19 EP7309 Signal D21 GNDR A20 D20 A19 D19 A18 D18 VDDR GNDR nTRST A17 D17 A16 D16 A15 D15 A14 D14 ...
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... EP7309 High-Performance, Low-Power System on Chip Table T. 204-Ball TFBGA Ball List (Continued) Die Pad Bond Pad Package Ball U2.155 154 C20 U2.156 155 E18 U2.157 156 B20 U2.158 157 C17 U2.159 158 B17 U2.160 159 A17 U2.161 160 C16 U2.162 161 B16 U2 ...
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... PBGA Package Characteristics 256-Ball PBGA Package Specifications Note: 1) For pin locations see Table 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7309 design, contact Cirrus Logic for the latest package information. DS507PP1 Signal GNDR GNDR GNDR Figure 13 ...
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... EP7309 High-Performance, Low-Power System on Chip Pin 1 Corner 17.00 (0.669) E1 ±0.20 (.008) 15.00 (0.590) ±0.20 (.008) 1.00 (0.040) REF 1.00 (0.040) REF 1.00 (0.040) 0. Places 32 17.00 (0.669) ±0.20 (.008) 15.00 (0.590) ±0.20 (.008) D1 Pin 1 Indicator TOP VIEW D 17.00 (0.669) 1.00 (0.040 ...
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... Main oscillator out Oscillator VDDOSC Oscillator power in, 2.5V power VSSIO Pad ground I/O ground nCS[5] O Chip select out VDDIO Pad power I/O ground nCS[3] O Chip select out nMOE O ROM, expansion OP enable VDDIO Pad power Digital I/O power, 3.3V N/C O EP7309 15 16 VSSIO A VDDIO nURESET B nPOR nEXTPWR C D[7] D[8] D D[9] D[10] E D[11] VDDIO F D[12] D[13] G D[14] D[15] H ...
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... EP7309 High-Performance, Low-Power System on Chip Table U. 256-Ball PBGA Ball Listing (Continued) Ball Location Name Type B7 DD[2] O LCD serial display data B8 CL[1] O LCD line clock B9 VDDCORE Core power Digital core power, 2.5V B10 D[1] I/O Data I/O B11 A[2] O System byte address B12 A[4] O System byte address B13 ...
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... Keyboard scanner column drive D[29] I/O Data I/O D[26] I/O Data I/O HALFWORD O Halfword access select output VSSIO Pad ground I/O ground D[22] I/O Data I/O D[23] I/O Data I/O VSSRTC RTC ground Real time clock ground RTCOUT O Real time clock oscillator output VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground VDDIO Pad power Digital I/O power, 3.3V EP7309 35 ...
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... EP7309 High-Performance, Low-Power System on Chip Table U. 256-Ball PBGA Ball Listing (Continued) Ball Location Name Type P6 VSSIO Pad ground I/O ground P7 VSSIO Pad ground I/O ground P8 VDDIO Pad power Digital I/O power, 3.3V P9 VSSIO Pad ground I/O ground P10 VDDIO Pad power Digital I/O power, 3.3V P11 VSSIO Pad ground I/O ground ...
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... Copyright 2001 Cirrus Logic (All Rights Reserved) High-Performance, Low-Power System on Chip Type Position I/O 17 I/O 20 I/O 23 I/O 26 I/O 29 I/O 32 I/O 35 I/O 38 I/O 41 I/O 44 I/O 47 I/O 50 I/O 53 I/O 56 I EP7309 37 ...
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... EP7309 High-Performance, Low-Power System on Chip Table V. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No 100 101 38 PBGA Signal Ball Ball T3 N1 nEXTFIQ ...
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... Type Position I/O 179 O 182 I/O 184 O 187 O 189 I/O 191 O 194 I/O 196 O 199 I/O 201 O 204 I/O 206 O 209 I/O 211 O 214 I/O 216 O 219 I/O 221 O 224 I/O 226 O 229 I/O 231 O 234 I/O 236 O 239 I/O 241 O 244 I/O 246 O 249 I/O 251 O 254 I/O 256 O 259 I/O 261 O 264 I/O 266 O 269 I/O 271 EP7309 39 ...
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... EP7309 High-Performance, Low-Power System on Chip Table V. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No. 148 150 151 152 153 154 155 156 161 162 163 164 165 166 169 170 171 172 173 175 176 177 178 179 184 185 ...
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... Table V. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No. 201 202 204 205 206 207 208 1) See EP7309 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. DS507PP1 PBGA Signal Ball Ball A7 D6 nMWE ...
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... EP7309 High-Performance, Low-Power System on Chip CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table W lists abbreviations and acronyms used in this data sheet. Table W. Acronyms and Abbreviations Acronym/ Definition Abbreviation A/D analog-to-digital ADC ...
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... Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7309 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “ ...
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... EP7309 High-Performance, Low-Power System on Chip ORDERING INFORMATION The order number for the device is: EP7309 — CV — C Note: Contact Cirrus Logic for up-to-date information on revisions the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. 44 Temperature Range: ...
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Notes • ...
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