Z86C83 Zilog., Z86C83 Datasheet - Page 30

• Manufacturer Part Number: Z86C83
• Description: Z8 MCU MICROCONTROLLERS
• Manufacturer: Zilog.

Z86C83/C84
Z8
Figure 27 shows the input circuit of the ADC. When
conversion starts the analog input voltage is connected to
the MSB and LSB flash converter inputs as shown in the
Input Impedance CKT diagram. Effectively, shunting 31
parallel internal resistance of the analog switches and
simultaneously charging 31 parallel 0.5 pF capacitors,
which is equivalent to seeing a 400 Ohms input impedance
Typical Z8 A/D Conversion Sequence
1. Set the register pointer to Extended Bank (C),that is,
2. Next, set ADE flag by loading ADC1 Control Register
30
®
MCU Microcontrollers
SRP #%0C instruction.
Bank (C) Register 9, bit 7. Also, load bits 0-4 of this
same register to select a AV
precision voltage divider connected to the A/D
resistive ladder can offset conversion dynamic range
to specified limits within the AV
loading Bank (C) Register 9, bits 0-4, with the
appropriate value it is possible to select from these
groups:
a. No Offset. The Converter Dynamic range is from
b. 35 Percent A
c. 50 Percent A
0V to 5.0V for AV
range is 1.75V - 5.0V for AV
range is 2.5V - 5.0V for AV
GND
GND
C Parasitic
R Source
Offset. The Converter Dynamic
Offset. The Converter Dynamic
CC
= 5.0V.
CC
CC
or A
CC
CC
= 5.0V.
= 5.0V.
and A
CMOS Switch
on Resistance
GND
Figure 27. Input Impedance of ADC
2 - 5 k
offset value. A
V Ref
V Ref
V Ref
GND
limits. By
C .5 pF
C .5 pF
C .5 pF
in parallel with a 16 pF capacitor. Other input stray
capacitance adds about 10 pF to the input load. For input
source resistances up to 2 kOhms can be used under
normal operating condition without any degradation of the
input settling time. For larger input source resistance,
longer conversion cycle time may be required to
compensate the input settling time problem.
3. Select one of the eight A/D inputs for conversion by
4. Set Bank (C) Register 8, bit 3 to enable A/D
5. Read the A/D result in Bank (C) Register A. Please
loading Bank (C) Register 8 with the desired attributes:
Bits 0 - 2 select an A/D input, bits 3 and 4 select A/D
conversion (or digital port I/O).
conversion. (This flag can be set concurrently with
step 3.) This flag is automatically reset when the A/D
conversion is completed, so a bit test can be
performed to determine A/D readiness if necessary.
note that the A/D result is not valid (indeterminate)
unless ADE flag (Register 9, bit 7) was previously set,
otherwise A/D converter output is tri-stated.
31 CMOS Digital
Comparators
DS96DZ80203