LT1812 Linear Technology, LT1812 Datasheet - Page 11

• Manufacturer Part Number: LT1812
• Description: 3mA/ 100MHz/ 750V/us Operational Amplifier with Shutdown
• Manufacturer: Linear Technology

SI PLIFIED
APPLICATIO S I FOR ATIO
junction temperature (T
temperature (T
Power dissipation is composed of two parts. The first is
due to the quiescent supply current and the second is due
to on-chip dissipation caused by the load current. The
worst-case load induced power occurs when the output
voltage is at 1/2 of either supply voltage (or the maximum
swing if less than 1/2 supply voltage). Therefore P
Example: LT1812CS8 at 70 C, V
Circuit Operation
The LT1812 circuit topology is a true voltage feedback
amplifier that has the slewing behavior of a current feed-
back amplifier. The operation of the circuit can be under-
stood by referring to the Simplified Schematic. The inputs
are buffered by complementary NPN and PNP emitter
followers that drive a 300
SHDN
W
LT1812CS8: T
P
P
P
T
V
V
JMAX
DMAX
DMAX
DMAX
+
–
= 70 C + (108mW)(80 C/W) = 79 C
= (V
= (V
= (10V)(4.5mA) + (2.5V)
+
+
A
R
) and power dissipation (P
– V
– V
B
J
= T
U
SCHEMATIC
–
–
)(I
)(I
–IN
A
BIAS
CONTROL
SMAX
SMAX
J
+ (P
) is calculated from the ambient
U
W
D
) + (V
) + (V
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
resistor. The input voltage
• 80 C/W) (Note 9)
S
+
+
= 5V, R
2
W
/2)
/100 = 108mW
– V
2
/R
OMAX
L
D
or
L
) as follows:
)(V
= 100
U
300
R1
OMAX
DMAX
/R
is:
L
)
appears across the resistor generating currents that are
mirrored into the high impedance node. Complementary
followers form an output stage that buffers the gain node
from the load. The bandwidth is set by the input resistor
and the capacitance on the high impedance node. The slew
rate is determined by the current available to charge the
gain node capacitance. This current is the differential input
voltage divided by R1, so the slew rate is proportional to
the input. Highest slew rates are therefore seen in the
lowest gain configurations. The RC network across the
output stage is bootstrapped when the amplifier is driving
a light or moderate load and has no effect under normal
operation. When driving capacitive loads (or a low value
resistive load) the network is incompletely bootstrapped
and adds to the compensation at the high impedance
node. The added capacitance slows down the amplifier
which improves the phase margin by moving the unity-
gain cross away from the pole formed by the output
impedance and the capacitive load. The zero created by the
RC combination adds phase to ensure that the total phase
lag does not exceed 180 degrees (zero phase margin) and
the amplifier remains stable. In this way, the LT1812 is
stable with up to 1000pF capacitive loads in unity gain, and
even higher capacitive loads in higher closed-loop gain
configurations.
+IN
C
R
C
C
C
LT1812
1812 SS
11
OUT