ispPAC-CLK55xx Lattice Semiconductor, ispPAC-CLK55xx Datasheet - Page 8

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ispPAC-CLK55xx

Manufacturer Part Number
ispPAC-CLK55xx
Description
In-System Programmable Clock Generator with Universal Fan-Out Buffer
Manufacturer
Lattice Semiconductor
Datasheet
Lattice Semiconductor
Output Test Loads
Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other
selected parameters as noted in the various tables of this data sheet.
Figure 3. CMOS Termination Load
Figure 4. HSTL/SSTL Termination Load
Figure 5. LVDS/LVPECL Termination Load
≈20Ω (HSTL)
40Ω (SSTL)
50Ω
Z=50Ω
Z=50Ω
Z=50Ω
8
Z=50Ω
5pF
ispClock5500 Family Data Sheet
1kΩ
50Ω
5pF
Termination Load
Termination Load
Equivalent
Termination Load
Equivalent
VT=1.65 V (SSTL3)
Equivalent
1.25 V (SSTL2)
0.75 V (HSTL)
50Ω
-Test
Point
Point
Test
5pF
5pF
Point
Test
0.1µF
50Ω
+Test
Point

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