AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 104

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.3.3
Figure 7-6
7-16
INT4 Control Register
(I4CON, Offset 40h)
(Master Mode)
The Am186ES and Am188ES microcontrollers provide INT4, an additional external
interrupt pin. This input behaves like INT3–INT0 on the 80C186 microcontroller with the
exception that INT4 is only intended for use as a fully nested-mode interrupt source. INT4
is not available in cascade mode.
This interrupt is assigned to interrupt type 10h. The Interrupt 4 Control register (see Figure
7-6) controls the operation of the INT4 signal.
INT4 Control Register
The value of I4CON at reset is 000Fh.
Bits 15–5: Reserved—Set to 0.
Bit 4: Level-Triggered Mode (LTM)—This bit determines whether the microcontroller
interprets an INT4 interrupt request as edge- or level-sensitive. A 1 in this bit configures
INT4 as an active High, level-sensitive interrupt. A 0 in this bit configures INT4 as a Low-
to-High, edge-triggered interrupt. In either case, INT4 must remain High until it is
acknowledged.
Bit 3: Mask (MSK)—This bit determines whether the INT4 signal can cause an interrupt.
A 1 in this bit masks this interrupt source, preventing INT4 from causing an interrupt. A 0
in this bit enables INT4 interrupts.
This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in Section
7.3.10 on page 7-24.
Bits 2–0: Priority (PR)—This field determines the priority of INT4 relative to the other
interrupt signals, as shown in Table 7-3 on page 7-18.
15
Interrupt Control Unit
Reserved
7
LTM
MSK
PR2
PR1
PR0
0