GAL20LV8D-5LJ Lattice Semiconductor, GAL20LV8D-5LJ Datasheet - Page 13

• Manufacturer Part Number: GAL20LV8D-5LJ
• Description: Low Voltage E2CMOS PLD Generic Array Logic
• Manufacturer: Lattice Semiconductor

Note: fmax with external feedback is calculated from measured
tsu and tco.
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
f
max with External Feedback 1/(
LOGIC
ARRAY
f
t
L O G I C
A R R A Y
su +
max with No Feedback
t
s u
t
h
FROM OUTPUT (O/Q)
UNDER TEST
*C
L
includes test fixture and probe capacitance.
R EG I S T E R
REGISTER
C L K
CLK
1.5ns 10% – 90%
t
t
GND to 3.0V
c o
See Figure
su+
1.5V
1.5V
t
co)
TEST POINT
Z
0
13
= 50 , C
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
Output Load Conditions (see figure)
Test Condition
A
B
C
L
= 35pF*
High Z to Active High at 1.9V
High Z to Active Low at 1.0V
Active High to High Z at 1.9V
Active Low to High Z at 1.0V
Specifications GAL20LV8
f
max with Internal Feedback 1/(
LOGIC
ARRAY
+1.45V
R
1
t
cf
t
pd
REGISTER
CLK
t
50
50
50
50
50
R
su+
1
t
cf)
35pF
35pF
35pF
35pF
35pF
C
L