GAL26CV12B-10LJ Lattice Semiconductor, GAL26CV12B-10LJ Datasheet - Page 11

• Manufacturer Part Number: GAL26CV12B-10LJ
• Description: High Performance E2CMOS PLD Generic Array Logic
• Manufacturer: Lattice Semiconductor

3-state levels are measured 0.5V from steady-state active
level.
GAL26CV12 Output Load Conditions (see figure)
f
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Definitions
Test Condition
A
B
C
f
Active High
Active Low
Active High
Active Low
max with External Feedback 1/(
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
LOGIC
ARRAY
L O G I C
A R R A Y
t
su +
f
max with No Feedback
t
s u
t
h
B-10/-15/-20
C-7/-10/-15
300
300
300
R
1
R EG I S T E R
REGISTER
C L K
CLK
390
390
390
390
390
1.5ns 10% – 90%
R
3ns 10% – 90%
2
t
t
GND to 3.0V
c o
See Figure
su+
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
11
FROM OUTPUT (O/Q)
UNDER TEST
Specifications GAL26CV12
*C
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
L
f
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
max with Internal Feedback 1/(
LOGIC
ARRAY
R
2
t
cf
t
+5V
pd
REGISTER
CLK
R
1
t
su+
C *
L
t
TEST POINT
cf)