AK4562VN Asahi Kasei Microsystems, AK4562VN Datasheet

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AK4562VN

Manufacturer Part Number
AK4562VN
Description
LOW POWER 20BIT CODEC WITH PGA
Manufacturer
Asahi Kasei Microsystems
Datasheet
ASAHI KASEI
MS0031-E-00
10. Power Supply
11. Power Supply Current
12. Ta = -20
13. Package : 28pin QFN
1. Resolution : 20bits
2. Recording Functions
3. Playback Functions
4. Power Management
5. ADC Characteristics
6. DAC Characteristics
7. 3-wire Serial Control, SSB I/F
8. Master Clock : 256fs/384fs
9. Audio Data Format : MSB First, 2’s compliment
2-Stereo Inputs Mixer
Analog Input PGA
Monaural Mixing
Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
Digital De-emphasis Filter (tc=50/15us, fs=32kHz, 44.1kHz and 48kHz)
Analog Output PGA
2 types Stereo Outputs (DAC and Analog Output PGA)
Input Level : 1.5Vpp = 0.6 x VREF@VREF=2.5V
S/(N+D) : 82dB
DR, S/N : 88dB
Output Level : 1.5Vpp = 0.6 x VREF@VREF=2.5V
S/(N+D) : 86dB
DR, S/N : 93dB
ADC : 20bit MSB justified, I
DAC : 16bit LSB justified, 20bit LSB justified, 24bit LSB justified, I
CODEC, PGA : 2.2
Digital I/F : 1.8
IPGA + ADC : 7mA
DAC + OPGA : 5.5mA
Size : 5.2mm x 5.2mm
Height : 1mm (max)
Pitch : 0.5mm
70 C
3.0V (typ. 2.5V)
3.0V (typ. 2.5V)
Low Power 20bit
2
S
FEATURES
- 1 -
CODEC with PGA
2
AK4562
S
[AK4562]
2000/05

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AK4562VN Summary of contents

Page 1

ASAHI KASEI 1. Resolution : 20bits 2. Recording Functions 2-Stereo Inputs Mixer Analog Input PGA Monaural Mixing Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz) 3. Playback Functions Digital De-emphasis Filter (tc=50/15us, fs=32kHz, 44.1kHz and 48kHz) Analog Output PGA 2 types Stereo ...

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LIN1 LIN2 RIN1 RIN2 OPGAL LOUT2 OPGAR ROUT2 ROUT1 LOUT1 ADC HPF DAC Control Register I/F Clock Divider CSN CCLK CDTI SSB MCLK (SCK) (SSI) VREF VA AGND VT VD DGND LRCK Audio I/F BCLK Controller SDTO SDTI PDN TST ...

Page 3

... ASAHI KASEI n Ordering Guide AK4562VN AKD4562 n Pin Layout OPGAR LOUT2 ROUT2 LIN1 RIN1 LIN2 RIN2 MS0031-E-00 -20 +70 C 28pin QFN (0.5mm pitch) Evaluation Board for AK4562 Top View [AK4562] CDTI LRCK MCLK TST BCLK SDTI ...

Page 4

ASAHI KASEI No. Pin Name I/O Function 1 OPGAR I Rch OPGA Input Pin 2 LOUT2 O Lch OPGA Output Pin 3 ROUT2 O Rch OPGA Output Pin 4 LIN1 I Lch #1 Input Pin 5 RIN1 I Rch #1 ...

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ASAHI KASEI (AGND, DGND=0V; Note 1) Parameter Power Supply Analog Digital 1 Digital 2 VD – VA |DGND – AGND| (Note 2) Input Current (Any Pin Except Supplies) Analog Input Voltage LIN1-2, RIN1-2, OPGAL, OPGAR, VREF pins Digital Input Voltage ...

Page 6

ASAHI KASEI (Ta=25 C; VA, VD, VT=2.5V; fs=44.1kHz; Signal Frequency=1kHz; Measurement frequency=10Hz 20kHz; unless otherwise specified) Parameter Resolution Input PGA Characteristics (IPGA): Input Voltage (LIN1, LIN2, RIN1, RIN2) (Note 5) Input Impedance +28dB Step Width -8dB -16dB -32dB -40dB ADC ...

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ASAHI KASEI Power Supplies Power Supply Current: VA+VD+VT Normal Operation (PDN=“H”) AD+DA (PM0=1, PM1=1, PM2=1, PM3=1) AD (PM0=1, PM1=1, PM2=0, PM3=0) DA (PM0=0, PM1=0, PM2=1, PM3=1) Power Down (PDN=“L”) Note : 11. In case of power-down mode, all digital input ...

Page 8

ASAHI KASEI (Ta=- VA, VD=2.2 3.0V, VT=1.8 Parameter ADC Digital Filter (Decimation LPF): Passband (Note 12) 0.1dB -1.0dB -3.0dB Stopband (Note 12) Passband Ripple Stopband Attenuation Group Delay (Note 13) Group Delay Distortion ADC Digital Filter (HPF): Frequency ...

Page 9

ASAHI KASEI (Ta=- VA, VD=2.2 3.0V, VT=1.8 Parameter Control Clock Frequency Master Clock (MCLK) 256fs: Frequency Pulse Width Low Pulse Width High 384fs: Frequency Pulse Width Low Pulse Width High Channel Clock (LRCK) Frequency Duty Cycle Audio Interface ...

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ASAHI KASEI n Timing Diagram MCLK LRCK BCLK LRCK BCLK SDTO tSDS SDTI LSB Figure 2. Audio Data Input/Output Timing (Audio I/F = No.0) CSN tCSS CCLK CDTI Figure 3. WRITE Command Input Timing (AKM) MS0031-E-00 1/fCLK tCLKH tCLKL 1/fs ...

Page 11

ASAHI KASEI CSN CCLK CDTI D4 Figure 4. WRITE Data Input Timing (AKM) SCK SSI Figure 5. WRITE Data Input Timing (SSB) PDN SDTO MS0031-E- tSCKL tSCKH tSIS tSIH tPW tPWV Figure 6. Reset Timing - 11 - ...

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ASAHI KASEI n System Clock The clocks that are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs ). The master clock (MCLK) should be synchronized with LRCK but the phase is free of care. The frequency of ...

Page 13

ASAHI KASEI LRCK BCLK(64fs) SDTO( SDTI(i) Don’t Care 23 SDTO-19:MSB, 0:LSB; SDTI-23:MSB, 0:LSB Lch Data LRCK BCLK(64fs) SDTO( SDTI( ...

Page 14

ASAHI KASEI Power Supply PDN pin PDN pin may be “L” at power-up. ADC Internal PD State AIN SDTO DAC Internal PD State SDTI AOUT1 (5) Control register INIT-2 W rite to register Inhibit-1 External clocks Figure 11. Power up ...

Page 15

ASAHI KASEI n Timing of Control Register AKM mode AKM mode is the data in I/F with 3-wire serial control, these data are included by Op-code (3bit), Address (LSB-first, 5bit) and Control data (LSB-first, 8bit). A side of transmitted data ...

Page 16

ASAHI KASEI n Register Map Addr Register Name 00H Input Select 01H Mode Control 1 02H Mode Control 2 MONO1 03H Input Analog PGA Control 04H Output Analog PGA Control ZEOP All registers are reset at PDN = “L”, then ...

Page 17

ASAHI KASEI Organizatio n of Power M a nagement bit circuit power-up PM0=1 PM1=1 PM2=1 PM3=1 2) REC monito r PM0=1 PM1=1 PM2=1 PM3 REC mo nitor PM0=1 PM1=1 PM2=0 PM3=0 4) PLA Y PM0=0 ...

Page 18

ASAHI KASEI Mode Control 2 Addr Register Name 02H Mode Control 2 MONO1 RESET MONO1-0: Monaural Mixing 00: Stereo (RESET) 01: (L+R)/2 10: LL 11: RR ZTM1-0: Setting of Zero Crossing Timeout for IPGA and OPGA 00: 256/fs 01: 512/fs ...

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ASAHI KASEI Input Analog PGA Control Addr Register Name 03H Input Analog PGA Control RESET ZEIP: Select IPGA zero crossing operation (0: Disable, 1: Enable) Writing to IPGA value at ZEIP = “1”, IPGA value of L/R channels changes by ...

Page 20

ASAHI KASEI About zero crossing operation Comparator for zero crossing detection in the AK4562 has offset. Therefore possible that IPGA (OPGA) value is changed by zero crossing timeout as zero crossing detection does not occur by a ...

Page 21

ASAHI KASEI Output Analog PGA Control Addr Register Name 04H Output Analog PGA Control ZEOP RESET ZEOP: Select OPGA zero crossing operation (0: Disable, 1: Enable) Writing to OPGA value at ZEOP = “1”, OPGA value of L/R channels changes ...

Page 22

ASAHI KASEI n Detail of functions (1) Input Analog PGA with Zero Crossing Detection Zero crossing is detected on L/R channels independently. If zero crossing is not detected, IPGA value changes by timeout. Timeout cycle can be set by ZTM1-0 ...

Page 23

ASAHI KASEI (4) Output Analog PGA with Zero Crossing Detection Zero crossing is detected on L/R channels independently. If zero crossing is not detected, OPGA value changes by timeout. Timeout cycle can be set by ZTM1-0 bit. For example, when ...

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ASAHI KASEI Write command When D/C bit is “1”, 8 bit data after information bits indicates a command ...

Page 25

ASAHI KASEI Example for access of Command and Data [WRITE Operation] Specific Device + AINC Specific Device + ADRSL Write Address Data Write Data Write Data Write Data Until coming the command of the next specific device after coming the ...

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ASAHI KASEI Figure 21 shows the system connection diagram. An evaluation board [AKD4562] is available which demonstrates application circuit, optimum layout, power supply arrangements and measurement results OPGAR 1 LOUT2 2 ROUT2 3 AK4562 LIN1 4 RIN1 5 ...

Page 27

ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4562 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied from analog supply in system. Alternatively if VA and VD are supplied separately, the power ...

Page 28

ASAHI KASEI 28pin QFN (Unit: mm) 5.2 ± 0.20 5.0 ± 0. 0.22 ± 0.05 Note : The black parts of back package should be open. n Package & Lead frame material Package molding compound: Lead ...

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... ASAHI KASEI These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein ...

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