ISPGDX240VA-9B388I Lattice Semiconductor, ISPGDX240VA-9B388I Datasheet - Page 16

• Manufacturer Part Number: ISPGDX240VA-9B388I
• Description: In-System Programmable 3.3V Generic Digital CrosspointTM
• Manufacturer: Lattice Semiconductor

The GDF File
The GDF file is a simple text description of the design
function, device and pin parameters. The file has four
parts: device selection, set and constant statements, a
pin section and a connection section. A sample file looks
like this:
// 32-Bit Data 3 to 1 Mux
DESIGN
PART ispGDX160V-7Q208;
PARAM SECURITY ON;
PARAM OPENDRAIN ON;
PARAM PULL HOLD;
SET BUS_A
SET BUS_B
SET BUS_C
SET BUS_D
INPUT
INPUT
INPUT
OUTPUT BUS_D
INPUT [oe]
INPUT [clk] {B36};
INPUT [sel1]
INPUT [sel0]
BEGIN
END
ispGDX Development System (Continued)
BUS_D.m0 = BUS_A;
BUS_D.m1 = BUS_B;
BUS_D.m2 = BUS_C;
BUS_D.m3 = VCC;
BUS_D.s1 = sel1;
BUS_D.s0 = sel0;
BUS_D.oe = oe;
BUS_D.clk = clk;
BUS_A
BUS_B
BUS_C
datamux;
[dataA31..dataA0];
[dataB31..dataB0];
[dataC31..dataC0];
[dataD31..dataD0];
{B37};
{A31..A0};
{B31..B0};
{C31..C0};
{D31..D0};
{B38};
{B39};
// USE OPEN DRAIN
// OPTION
// USE BUS HOLD
// LATCH OPTION
// Default all
// outputs to VCC
16
This example shows a simple, but complete, 32-bit 3:1
MUX design. Once completed, the compiler takes over.
Powerful Syntax
Lattice’s ispGDX Design System uses simple, but power-
ful, syntax to easily define a design. The !(bang) operator
controls pin polarity and can be used in both the pin and
connection sections of the design definition. Dot exten-
sions define data inputs, select controls for the 4:1
multiplexor, and control inputs of sequential elements
and tri-state buffers. Dot extensions are .M# (MUX Input),
.S# (MUX Select), and control functions, such as .CLK,
.EN, .OE and .A (shown in adjacent table). Pin Attributes
are assigned in the pin section of the GDF as well.
SLOWSLEW selects the slow slew rate for an output
buffer. The Pull parameter can be used to select the
internal pull-up or bus hold latch. OPEN drain can be
used to select open drain operation. The COMB attribute
distinguishes the structure for bidirectional pins. If COMB
is used, the input register, or latch, of an output buffer will
be applied to bidirectional pins.
Please consult the ispGDX Development System Manual
for full details.
ispGDX GDF File Dot Extensions
Specifications ispGDX240VA
Selection
Control
Output
Type
MUX
Input
MUX
MUX
Dot Ext.
.CLK
.M0
.M1
.M2
.M3
.EN
.OE
.CE
.S0
.S1
.A
MUXA Data input to 4:1 MUX
MUXB Data input to 4:1 MUX
MUXC Data Input to 4:1 MUX
MUXD Data input to 4:1 MUX
MUX0 Selection input to 4:1 MUX
MUX1 Selection input to 4:1 MUX
Clock for a register
Latch enable for a latch signal
Output enable for 3-state output
or bidirectional signal
Clock enable for register clock
Adjacent MUX output of an I/O cell
Description
ispGDXV Dot Ext