RTC4573 Epson Company, RTC4573 Datasheet - Page 7

• Manufacturer Part Number: RTC4573
• Description: Serial RTC with Alarm and Timer
• Manufacturer: Epson Company

1.5. Control register1 ( Reg-E )
TI / TPbits: ( Interrupt Signal Output Mode Select. Timer-Interrupt / Timer-Periodic )
output mode of timer signaling.
AF / TF bits: ( Alarm Flag / Timer Flag )
AIE,TIE bits: ( Alarm / Timer Interrupt Enable )
TIE corresponds to a timer, and AIRQ terminal is set in case of "0" AIE bit by Hi-Z, and TIRQ terminal is set in case of
"0" TIE bit by Hi-Z.
1.6 Control register 2 (register F )
· TEST bit : This is a test bit for Seiko-Epson?s use.
Always set this bit to "0". When writing to the other bits in the CF register, be careful not to accidentally write a "1" to
this bit. This bit is cleared by setting CE low.
· STOP bit
If this bit is set to "1", timekeeping stops (after 4KHz). If this bit is set back to "0", timekeeping resumes.
· RESET bit
Setting this bit to "1" resets the counter below the seconds counter, stopping timekeeping. If a "1" is written to this bit,
it is cleared either by writing a "0" to this bit again with the auto increment function, or by setting CE low.
The only effect on timekeeping precision is a maximum error 61 [micro]s. This bit is unaffected by the status of other
bits.
· HOLD bit
and if there was a carry to the seconds counter while HOLD = 1, compensation (by means of adding one second) is
made immediately (within 0 to 122 [micro]s) after HOLD is released.This bit is cleared by writing a "0" to it.
When alarm occurs, AF bit is set in "1", and a timer is set in "1" at 0 o?clock, and TF bit can?t write in "1" at both bit.
It is decided whether IRQ terminal drives it when alarm, timer interrupt occurred, and AIE corresponds in alarm, and
This bit stops carries to the ones digit of the seconds counter. Timekeeping continues below the seconds counter,
TI / TP
Address
Address
bit
F
E
written in "0" at TF bit when turn into interrupt
mode, and timer interrupt occurs, and, but,
timer interrupt signal does it with TIE=1
TIRQ terminal is maintained by "L" till it is
bit 7
bit 7
*
*
TEST
bit 6
bit 6
*
STOP
0
bit 5
bit 5
*
RESET
TI/TP
bit 4
bit 4
Page-7
HOLD
bit 3
bit 3
AF
repeatedly. When timer interrupt occurs,
TIRQ terminal is set at "L" immediately and,
but, does it with TIE=1. TF bit is set in "1",
and TIRQ terminal is set in Hi-Z after
approximately 3.9 m s, and TF bit holds "1" till
it is write clear by "0".
Timer interrupt signaling is set in a mode
bit 2
bit 2
TF
*
bit 1
bit 1
AIE
*
1
bit 0
bit 0
TIE
*
Aug.1998