27C04A Microchip Technology, 27C04A Datasheet - Page 6

• Manufacturer Part Number: 27C04A
• Description: 4K (512 x 8) CMOS EEPROM
• Manufacturer: Microchip Technology

28C04A
2.0
The Microchip Technology Inc. 28C04A has four basic
modes of operation—read, standby, write inhibit, and
byte write—as outlined in the following table.
2.1
The 28C04A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to the
output pins independent of device selection. Assuming
that addresses are stable, address access time (t
is equal to the delay from CE to output (t
available at the output tOE after the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least t
2.2
The 28C04A is placed in the standby mode by applying
a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, inde-
pendent of the OE input.
2.3
In order to ensure data integrity, especially during criti-
cal power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal V
the initiation of non-volatile programming operation
when V
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10 ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (V
DS11126F-page 6
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
X = Any TTL level.
Operation
Mode
CC
DEVICE OPERATION
Read Mode
Standby Mode
Data Protection
is less than the V
CC
CE
Automatic Before Each “Write”
detect (3.3 volts typical) will inhibit
H
H
X
X
L
L
ACC
-t
CC
OE
IE
H
X
X
X
L
L
detect circuit trip.
.
WE
CC
H
H
X
X
X
L
).
CE
). Data is
High Z
High Z
High Z
High Z
D
D
I/O
OUT
ACC
IN
)
2.4
The 28C04A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and initi-
ated by a low going pulse on the WE pin. On the falling
edge of WE, the address information is latched. On ris-
ing edge, the data and the control pins (CE and OE) are
latched.
2.5
The 28C04A features Data polling to signal the comple-
tion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 are indetermin-
able). After completion of the write cycle, true data is
available. Data polling allows a simple read/compare
operation to determine the status of the chip eliminating
the need for external hardware.
2.6
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data.
Write Mode
Data Polling
Chip Clear
1996 Microchip Technology Inc.