SAA4978 Philips, SAA4978 Datasheet - Page 2

• Manufacturer Part Number: SAA4978
• Description: Picture Improved Combined Network PICNIC
• Manufacturer: Philips

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The integrated 16 : 9 compressor is an IC which
compresses the active part of a video line by a factor of
from, for example, 52 s to 39 s. This is necessary to
display 4:3 video software on a 16 : 9 tube in the correct
proportion. The capacitively coupled video inputs are Y,
(B Y) and (R Y).
QUICK REFERENCE DATA
Voltages for video signals are peak-to-peak values for 75% colour bars. All voltages are referenced to
V
ORDERING INFORMATION
1995 Oct 05
V
V
V
V
V
V
V
V
V
SAA4981
SAA4981T
EEA
Fixed horizontal compression by a factor of
video standards
Three fixed screen positions (left, centre and right)
5 MHz bandwidth
Bypass function
Inputs for luminance and chrominance of side panels
Standard video inputs and outputs (Y, (B Y) and (R Y))
Horizontal and vertical sync signals are not processed
Pre filters and post filters on chip.
CCA
CCD
iY(p-p)
iU(p-p)
iV(p-p)
iHREF
oY(p-p)
oU(p-p)
oV(p-p)
TYPE NUMBER
Monolithic integrated 16 : 9 compressor
SYMBOL
= V
EED
= 0 V.
analog supply voltage
digital supply voltage
Y input voltage (peak-to-peak value)
(B Y) input voltage (peak-to-peak value)
(R Y) input voltage (peak-to-peak value)
input HREF top pulse
YOUT output voltage (peak-to-peak value)
(B Y)OUT output voltage (peak-to-peak value)
(R Y)OUT output voltage (peak-to-peak value)
DIP24
SO24
NAME
PARAMETER
plastic dual in-line package; 24 leads (600 mil)
plastic small outline package; 24 leads; body width 7.5 mm
4
3
for most
4
3
2
The synchronisation input HREF is a line frequency
reference signal. The bandwidth of the IC is up to 5 MHz
and the signal delay is realized with SC Line Memories
(Switched Capacitors Line Memories). The output of the
16 : 9 compressor also has the format Y, (B Y) and (R Y)
and provides the following two possibilities:
1. Bypass function (the input signal is not compressed)
2. Compressed video by a factor of
The horizontal compression is a time discrete and
amplitude continuous signal processing. This provides pre
and post filters which are realized on-chip. The internal
clock generation is achieved with a 54 MHz horizontal PLL
which is synchronized to the positive edge of the HREF
signal. The function of the IC is controlled by the three
control signals CTRL1, CTRL2 and CTRL3.
DESCRIPTION
PACKAGE
fixed screen positions (left, centre and right). The
luminance and chrominance of the side panels are
determined by the external signals YSIDE, BYSIDE
and RYSIDE.
4.75
4.75
3.0
MIN.
5.0
5.0
0.32
1.33
1.05
0.32
1.33
1.05
TYP.
Preliminary specification
5.5
5.5
0.45
1.9
1.5
6.5
0.5
2.1
1.7
4
MAX.
3
with three different
SAA4981
SOT101-1
SOT137-1
VERSION
V
V
V
V
V
V
V
V
V
UNIT