54ABT16374W-QML National Semiconductor, 54ABT16374W-QML Datasheet

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54ABT16374W-QML

Manufacturer Part Number
54ABT16374W-QML
Description
16-Bit D Flip-Flop with TRI-STATE Outputs
Manufacturer
National Semiconductor
Datasheet
PrintDate=1998/07/14 PrintTime=11:05:34 43604 ds100224 Rev. No. 1 cmserv
© 1998 National Semiconductor Corporation
54ABT16374
16-Bit D Flip-Flop with TRI-STATE
General Description
The ABT16374 contains sixteen non-inverting D flip-flops
with TRI-STATE outputs and is intended for bus oriented ap-
plications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
Ordering Code:
Connection Diagram
TRI-STATE
54ABT16374W-QML
®
is a registered trademark of National Semiconductor Corporation.
Commercial
Pin Assignment for Cerpack
DS100224
DS100224-2
WA48A
Package
Number
48-Lead Cerpack
Features
n Separate control logic for each byte
n 16-bit version of the ABT374
n Edge-triggered D-type inputs
n Buffered Positive edge-triggered clock
n High impedance glitch free bus loading during entire
n Non-destructive hot insertion capability
n Guaranteed latch-up protection
n Standard Microcircuit Drawing (SMD) 5962-9320101
Logic Symbol
Pin Description
OE
CP
D
O
Names
power up and power down cycle
0
0
–D
Pin
–O
n
n
15
15
®
Package Description
Outputs
TRI-STATE Output Enable Input (Active Low)
Clock Pulse Input (Active Rising Edge)
Data Inputs
TRI-STATE Outputs
Proof
Description
www.national.com
July 1998
DS100224-1
1
1

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54ABT16374W-QML Summary of contents

Page 1

... TRI-STATE outputs and is intended for bus oriented ap- plications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. Ordering Code: Commercial 54ABT16374W-QML Connection Diagram Pin Assignment for Cerpack TRI-STATE ® registered trademark of National Semiconductor Corporation. ...

Page 2

Functional Description The ABT16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The device is byte controlled with each byte functioning iden- tically, but independent of the other. The control pins can be shorted together ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic V Pin Potential to CC Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State ...

Page 4

DC Electrical Characteristics Symbol Parameter V Quiet Output Maximum Dynamic V OLP V Quiet Output Minimum Dynamic V OLV Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output ...

Page 5

DS100224-6 * Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 3. Test Input Pulse Requirements PrintDate=1998/07/14 PrintTime=11:05:38 43604 ds100224 Rev. No. 1 cmserv Amplitude Rep Rate ...

Page 6

... Fax: +49 (0) 1 80-530 85 86 Response Group Email: europe.support@nsc.com Tel: 65-2544466 Deutsch Tel: +49 (0) 1 80-530 85 85 Fax: 65-2504466 English Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 Proof National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 6 ...

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