54ABT16500W-QML National Semiconductor, 54ABT16500W-QML Datasheet

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54ABT16500W-QML

Manufacturer Part Number
54ABT16500W-QML
Description
18-Bit Universal Bus Transceivers with TRI-STATE Outputs
Manufacturer
National Semiconductor
Datasheet
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv
© 1998 National Semiconductor Corporation
54ABT16500
18-Bit Universal Bus Transceivers with TRI-STATE
Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transparent,
latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is
stored in the latch/flip-flop on the high-to-low transition of
CLKAB. Output-enable OEAB is active-high. When OEAB is
high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, and CLKBA. The output enables are complementary
(OEAB is active high and OEBA is active low).
Ordering Code
TRI-STATE
54ABT16500W-QML
®
is a registered trademark of National Semiconductor Corporation.
Military
DS100225
WA56A
Package
Number
56-Lead Cerpack
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
n Combines D-Type latches and D-Type flip-flops for
n Flow-through architecture optimizes PCB layout
n Guaranteed latch-up protection
n High impedance glitch free bus loading during entire
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9687001
operation in transparent, latched, or clocked mode
power up and power down cycle
Package Description
Proof
®
www.national.com
July 1998
1
1

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54ABT16500W-QML Summary of contents

Page 1

... Data flow for similar to that but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). Ordering Code Military 54ABT16500W-QML TRI-STATE ® registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100225 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev ...

Page 2

Connection Diagram Function Table (Note 1) Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before ...

Page 3

Logic Diagram PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv 3 Proof DS100225-2 www.national.com 3 ...

Page 4

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic V Pin Potential to CC Ground Pin Input Voltage (Note 4) Input Current (Note 4) Voltage Applied to Any Output in the Disabled or Power-off State ...

Page 5

DC Electrical Characteristics Symbol Parameter V Quiet Output Maximum Dynamic V OLP V Quiet Output Minimum Dynamic V OLV Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output ...

Page 6

AC Operating Requirements Symbol Parameter t (H) Pulse Width, CLKAB w t (L) or CLKBA, High or Low w Capacitance Symbol C Input Capacitance IN C (Note 8) Output Capacitance I/O is measured at frequency MHz per ...

Page 7

AC Loading DS100225-3 *Includes jig and probe capacitance. FIGURE 1. Standard AC Test Load = 1.5V FIGURE Input Pulse Requirements Amplitude Rep. Rate t W 3.0V 1 MHz 500 ns 2.5 ns FIGURE 3. Test Input Signal ...

Page 8

... Email: europe.support@nsc.com Tel: 65-2544466 Deutsch Tel: +49 (0) 1 80-530 85 85 Fax: 65-2504466 English Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 Proof Book Extract End National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 8 ...

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