K7N161801A-Q(F)C(I)13 Samsung semiconductor, K7N161801A-Q(F)C(I)13 Datasheet - Page 3

• Manufacturer Part Number: K7N161801A-Q(F)C(I)13
• Description: 512Kx36 & 1Mx18 Pipelined NtRAM
• Manufacturer: Samsung semiconductor

K7N803601B
K7N801801B
LOGIC BLOCK DIAGRAM
FEATURES
FAST ACCESS TIMES
256Kx32 & 256Kx36 & 512Kx18-Bit Pipelined NtRAM
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
• Α interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A
• Operating in commercial and industrial temperature range.
A [0:17] or
A [0:18]
CLK
CKE
CS
CS
CS
ADV
WE
BW
(x=a,b,c,d or a,b)
OE
ZZ
DQa
DQPa ~ DQPd
Cycle Time
Clock Access Time
Output Enable Access Time
or 2.5V+0.4V/-0.125V for 2.5V I/O.
contention .
1
2
2
x
0
~ DQd
PARAMETER
7
or DQa0 ~ DQb8
K
REGISTER
ADDRESS
Symbol
t
t
t
CYC
CD
OE
A
2
~A
17
-16
6.0
3.5
3.5
or A2~A18
REGISTER
ADDRESS
WRITE
LBO
A
0
~A
-13
7.5
4.2
3.8
1
CONTROL
256Kx36 & 512Kx18 Pipelined NtRAM
LOGIC
Unit
COUNTER
ADDRESS
ns
ns
ns
NtRAM
and its architecture and functionalities are supported by NEC and Toshiba.
BURST
REGISTER
ADDRESS
- 3 -
TM
WRITE
and No Turnaround Random Access Memory are trademarks of Samsung,
GENERAL DESCRIPTION
The K7N803601B and K7N801801B are
The NtRAM
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803601B and K7N801801B are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP and Multiple power and ground pins mini-
mize ground bounce.
9,437,184 bits Synchronous Static SRAMs.
A′
0
~A′
1
TM
, or No Turnaround Random Access Memory uti-
TM
36 or 18
K
K
REGISTER
REGISTER
DATA-IN
DATA-IN
256Kx36 , 512Kx18
MEMORY
ARRAY
K
REGISTER
OUTPUT
BUFFER
Nov. 2003
Rev 3.0
TM